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yannickreiss
2024-08-07 18:30:30 +02:00
parent b3cc87a6d3
commit 1772ac2af2
14 changed files with 249 additions and 218 deletions
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34
tb/tb_cpu.vhd
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@@ -22,11 +22,43 @@ architecture Behavioral of cpu_tb is
-- Clock period definitions
constant clk_period : time := 10 ns;
-- CPU and RAM constraints
signal cpu_reset : std_logic := '0';
signal cpu_instruction : word := (others => '0');
signal cpu_data : word := (others => '0');
signal ram_enable : std_logic := '0';
signal instr_pointer : ram_addr_t := (others => '0');
signal ram_address : ram_addr_t := (others => '0');
signal ram_data : word := (others => '0');
signal ram_cut_zeros : ram_addr_t := (others => '0');
signal instr_pointer_zeros : ram_addr_t := (others => '0');
begin
ram_cut_zeros <= "00000000000000000000" & ram_address(11 downto 0);
instr_pointer_zeros <= "00000000000000000000" & instr_pointer(11 downto 0);
-- Instantiate the Unit Under Test (UUT)
uut : entity work.cpu(implementation)
port map (clk => clk);
port map (clk => clk,
rst => cpu_reset,
instruction_read => cpu_instruction,
ram_read_data => cpu_data,
ram_enable_writing => ram_enable,
instruction_pointer => instr_pointer,
data_address => ram_address,
ram_write_data => ram_data
);
rut : entity work.ram (behavioral)
port map(clk => clk,
instructionAddr => instr_pointer_zeros,
dataAddr => ram_cut_zeros,
writeEnable => ram_enable,
dataIn => ram_data,
instruction => cpu_instruction,
dataOut => cpu_data
);
-- Clock process definitions
clk_process : process

16
tb/tb_imm.vhd
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@@ -13,8 +13,8 @@ library std;
use std.textio.all;
-- Entity imm_tb: dummy entity
entity imm_tb is
end imm_tb;
entity imm_tb is
end imm_tb;
architecture testing of imm_tb is
@@ -32,10 +32,10 @@ architecture testing of imm_tb is
begin
uut : entity work.imm
port map(
instruction => s_instruction,
opcode => s_opcode,
immediate => s_immediate
instr => s_instruction,
opcode => s_opcode,
immediate => s_immediate
);
-- Process clk_process operating the clock
@@ -65,10 +65,10 @@ begin
s_opcode <= uADDI;
wait for 10 ns;
-- addi x2, x0, 1
s_instruction <= x"00100113";
s_opcode <= uADDI;
s_opcode <= uADDI;
wait;

50
tb/tb_ram.vhd
View File

@@ -14,39 +14,39 @@ end ram_tb;
architecture Behavioral of ram_tb is
-- Clock
signal clk : std_logic;
signal clk : std_logic := '0';
-- Inputs
signal addr_a : std_logic_vector(ram_addr_size - 1 downto 0);
signal write_b : std_logic_vector(1-1 downto 0);
signal addr_b : std_logic_vector(ram_addr_size - 1 downto 0);
signal data_write_b : std_logic_vector(wordWidth - 1 downto 0);
signal addr_a : std_logic_vector(ram_addr_size - 1 downto 0) := (others => '0');
signal write_b : std_logic := '0';
signal addr_b : std_logic_vector(ram_addr_size - 1 downto 0) := (others => '0');
signal data_write_b : std_logic_vector(wordWidth - 1 downto 0) := (others => '0');
-- Outputs
signal data_read_a : std_logic_vector(wordWidth - 1 downto 0);
signal data_read_b : std_logic_vector(wordWidth - 1 downto 0);
signal data_read_a : std_logic_vector(wordWidth - 1 downto 0) := (others => '0');
signal data_read_b : std_logic_vector(wordWidth - 1 downto 0) := (others => '0');
-- Clock period definitions
constant clk_period : time := 10 ns;
-- Unittest Signale
signal tb_addr_a : integer;
signal tb_addr_b : integer;
signal tb_test_v : std_logic_vector(wordWidth - 1 downto 0);
signal tb_check_v : std_logic_vector(wordWidth - 1 downto 0);
signal tb_validate : std_logic;
signal tb_addr_a : integer := 0;
signal tb_addr_b : integer := 0;
signal tb_test_v : std_logic_vector(wordWidth - 1 downto 0) := (others => '0');
signal tb_check_v : std_logic_vector(wordWidth - 1 downto 0) := (others => '0');
signal tb_validate : std_logic := '0';
begin
-- Instantiate the Unit Under Test (UUT)
uut : entity work.ram(Behavioral)
port map (clk => clk,
instructionAdr => addr_a,
dataAdr => addr_b,
writeEnable => write_b,
dataIn => data_write_b,
instruction => data_read_a,
dataOut => data_read_b);
port map (clk => clk,
instructionAddr => addr_a,
dataAddr => addr_b,
writeEnable => write_b,
dataIn => data_write_b,
instruction => data_read_a,
dataOut => data_read_b);
-- Clock process definitions
clk_process : process
@@ -68,17 +68,17 @@ begin
wait until rising_edge(clk);
-- manual test
addr_a <= "001101001110";
addr_b <= "011100110010";
write_b <= "1";
addr_a <= "00000000000000000000000000000110";
addr_b <= "00000000000000000000000000000010";
write_b <= '1';
wait for 10 ns;
-- Testing Mem
tb_validate <= '1';
write_b <= std_logic_vector(to_unsigned(1, 1));
for test_case in 0 to 1000 loop
for tb_addr in 0 to 4096 loop
write_b <= '1';
for test_case in 0 to 12 loop
for tb_addr in 0 to 12 loop
-- assign test values
tb_test_v <= std_logic_vector(to_unsigned(tb_addr, wordWidth));
tb_check_v <= std_logic_vector(to_unsigned(tb_addr, wordWidth));

49
tb/tb_riscv.vhd Normal file
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@@ -0,0 +1,49 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.riscv_types.all;
library std;
use std.textio.all;
entity cpu_tb is
end cpu_tb;
architecture Behavioral of cpu_tb is
-- Clock
signal clk : std_logic;
-- Inputs
-- Outputs
-- Clock period definitions
constant clk_period : time := 10 ns;
begin
-- Instantiate the Unit Under Test (UUT)
uut : entity work.cpu(implementation)
port map (clk => clk);
-- Clock process definitions
clk_process : process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Process stim_proc stimulate uut
stim_proc : process -- runs only, when changed
variable lineBuffer : line;
begin
write(lineBuffer, string'("Start the simulator"));
writeline(output, lineBuffer);
wait for 0 ns;
end process;
end architecture;