From 59cb94480ed3a64571f005e412b9ab04eaafbc95 Mon Sep 17 00:00:00 2001
From: yannickreiss <yannick.reiss@protonmail.ch>
Date: Thu, 8 Aug 2024 08:04:29 +0200
Subject: [PATCH] Reset in Register

---
 src/registers.vhd | 24 ++++++++++--------------
 1 file changed, 10 insertions(+), 14 deletions(-)

diff --git a/src/registers.vhd b/src/registers.vhd
index 7bd40b6..2156811 100644
--- a/src/registers.vhd
+++ b/src/registers.vhd
@@ -40,23 +40,19 @@ architecture structure of registers is
 begin
 
     -- react only on clock changes
-    process (clk)                       -- runs only, when clk changed
-    begin
-        if rising_edge(clk) then
-            -- check if write is enabled
-            if to_integer(unsigned(write_enable)) = 1 then
-                -- write data_in to wr_idx
-                registerbench(to_integer(unsigned(wr_idx))) <= data_in;
-            end if;
-            registerbench(0) <= std_logic_vector(to_unsigned(0, wordWidth));
-        end if;
-    end process;
-
-    -- reset if reset is activated
-    process (reset)
+    process (clk, reset)                -- runs only, when clk changed
     begin
         if falling_edge(reset) then
             registerbench <= initRegs;
+        else
+            if rising_edge(clk) then
+                -- check if write is enabled
+                if to_integer(unsigned(write_enable)) = 1 then
+                    -- write data_in to wr_idx
+                    registerbench(to_integer(unsigned(wr_idx))) <= data_in;
+                end if;
+                registerbench(0) <= std_logic_vector(to_unsigned(0, wordWidth));
+            end if;
         end if;
     end process;