From 83c663241555a774768213fe456630ec34a31c35 Mon Sep 17 00:00:00 2001 From: yannickreiss Date: Thu, 8 Aug 2024 06:05:54 +0200 Subject: [PATCH] Implement reset of the processor --- src/cpu.vhd | 16 +- src/pc.vhd | 27 ++-- src/registers.vhd | 14 +- tb/tb_cpu.vhd | 9 +- tb/tb_pc.vhd | 207 ++++++++++++------------- tb/tb_reg.vhd | 377 +++++++++++++++++++++++----------------------- 6 files changed, 343 insertions(+), 307 deletions(-) diff --git a/src/cpu.vhd b/src/cpu.vhd index 8fe0c2d..92d158d 100644 --- a/src/cpu.vhd +++ b/src/cpu.vhd @@ -29,6 +29,7 @@ architecture implementation of cpu is component pc port( clk : in std_logic; -- Clock input for timing + reset : in std_logic; en_pc : in one_bit; -- activates PC addr_calc : in ram_addr_t; -- Address from ALU doJump : in one_bit; -- Jump to Address @@ -66,6 +67,7 @@ architecture implementation of cpu is component registers port( clk : in std_logic; -- input for clock (control device) + reset : in std_logic; en_reg_wb : in one_bit; -- enable register write back (?) data_in : in word; -- Data to be written into the register wr_idx : in reg_idx; -- register to write to @@ -133,8 +135,8 @@ architecture implementation of cpu is signal X_addr_calc : ram_addr_t; -- Clock signals - signal reset : std_logic; - signal locked : std_logic; + signal reset : std_logic := '0'; + signal locked : std_logic := '0'; ------------------------- -- additional ALU signals @@ -151,6 +153,7 @@ begin -- External assignments s_clock <= clk; + reset <= rst; ram_enable_writing <= s_ram_enable; instruction_pointer <= s_instAddr; data_address <= s_data_in_addr; @@ -170,6 +173,7 @@ begin registers_RISCV : registers port map( clk => s_clock, + reset => reset, en_reg_wb => s_reg_wb_enable, data_in => reg_data_in, wr_idx => s_idx_wr, @@ -190,6 +194,7 @@ begin pc_RISCV : pc port map( clk => s_clock, + reset => reset, en_pc => s_pc_enable, addr_calc => X_addr_calc, doJump => s_pc_jump_enable, @@ -243,7 +248,6 @@ begin when others => aluIn1 <= s_reg_data1; end case; - -- TODO: why line from pc to alu inp1? -- connect input 2 case s_opcode is when uADDI | uSLTI | uSLTIU | uXORI | uORI | uANDI => aluIn2 <= s_immediate; @@ -313,7 +317,7 @@ begin end process; -- pc cycle control - pc_cycle_control : process(s_clock) + pc_cycle_control : process(s_clock, reset) begin if rising_edge(s_clock) then case s_cycle_cnt is @@ -323,6 +327,10 @@ begin when stEXEC => s_cycle_cnt <= stWB; when others => s_cycle_cnt <= stIF; end case; + else + if falling_edge(reset) then + s_cycle_cnt <= stIF; + end if; end if; end process pc_cycle_control; diff --git a/src/pc.vhd b/src/pc.vhd index 4b595d0..61c0479 100644 --- a/src/pc.vhd +++ b/src/pc.vhd @@ -12,35 +12,44 @@ use work.riscv_types.all; -- Entity PC: entity defining the pins and ports of the programmcounter entity pc is port (clk : in std_logic; -- Clock input for timing + reset : in std_logic; en_pc : in one_bit; -- activates PC addr_calc : in ram_addr_t; -- Address from ALU doJump : in one_bit; -- Jump to Address addr : out ram_addr_t -- Address to Decoder - ); + ); end PC; architecture pro_count of pc is - signal addr_out : ram_addr_t := (others => '0'); - signal addr_out_plus : ram_addr_t := (others => '0'); + signal addr_out : ram_addr_t := (others => '0'); + signal addr_out_plus : ram_addr_t := (others => '0'); begin process (clk) begin if rising_edge(clk) then if en_pc = "1" then -- count - if doJump = "1" then - addr_out <= addr_calc; + if doJump = "1" then + addr_out <= addr_calc; -- jump else - addr_out <= addr_out_plus; + addr_out <= addr_out_plus; end if; end if; end if; end process; - + + process (reset) + begin + if falling_edge(reset) then + addr_out <= (others => '0'); + addr_out_plus <= (others => '0'); + end if; + end process; + addr_out_plus <= (std_logic_vector(to_unsigned(to_integer(unsigned(addr_out)) + 4, ram_addr_size))); - addr <= addr_out; - + addr <= addr_out; + end pro_count; diff --git a/src/registers.vhd b/src/registers.vhd index 458db6a..7bd40b6 100644 --- a/src/registers.vhd +++ b/src/registers.vhd @@ -22,6 +22,7 @@ entity registers is generic (initRegs : regFile := (others => (others => '0'))); port( clk : in std_logic; -- input for clock (control device) + reset : in std_logic; en_reg_wb : in one_bit; -- enable register write back (?) data_in : in word; -- Data to be written into the register wr_idx : in reg_idx; -- register to write to @@ -50,8 +51,17 @@ begin registerbench(0) <= std_logic_vector(to_unsigned(0, wordWidth)); end if; end process; + + -- reset if reset is activated + process (reset) + begin + if falling_edge(reset) then + registerbench <= initRegs; + end if; + end process; + -- read from both reading registers - r1_out <= registerbench(to_integer(unsigned(r1_idx))); - r2_out <= registerbench(to_integer(unsigned(r2_idx))); + r1_out <= registerbench(to_integer(unsigned(r1_idx))); + r2_out <= registerbench(to_integer(unsigned(r2_idx))); end structure; diff --git a/tb/tb_cpu.vhd b/tb/tb_cpu.vhd index d6ab475..d1f5b08 100644 --- a/tb/tb_cpu.vhd +++ b/tb/tb_cpu.vhd @@ -13,11 +13,9 @@ end cpu_tb; architecture Behavioral of cpu_tb is - -- Clock + -- Clock and Reset signal clk : std_logic; - -- Inputs - -- Outputs -- Clock period definitions constant clk_period : time := 10 ns; @@ -76,6 +74,11 @@ begin write(lineBuffer, string'("Start the simulator")); writeline(output, lineBuffer); + wait for 100 ns; + cpu_reset <= '1'; + wait for 17 ns; + cpu_reset <= '0'; + wait; end process; end architecture; diff --git a/tb/tb_pc.vhd b/tb/tb_pc.vhd index 0ec38b6..cdea577 100644 --- a/tb/tb_pc.vhd +++ b/tb/tb_pc.vhd @@ -18,116 +18,119 @@ end pc_tb; -- Architecture testing of pc_tb: testing calculations architecture testing of pc_tb is - -- clock definition - signal clk : std_logic; - constant clk_period : time := 10 ns; + -- clock definition + signal clk : std_logic; + constant clk_period : time := 10 ns; + + -- Inputs pc + signal en_pc : one_bit; + signal addr_calc : ram_addr_t; + signal doJump : one_bit; + + -- Outputs pc + signal addr : ram_addr_t; + + -- unittest signals pc + signal addr_calc_tb : ram_addr_t; + + signal reset : std_logic; - -- Inputs pc - signal en_pc : one_bit; - signal addr_calc : ram_addr_t; - signal doJump : one_bit; - - -- Outputs pc - signal addr : ram_addr_t; - - -- unittest signals pc - signal addr_calc_tb : ram_addr_t; - begin - -- Entity work.pc(pro_count): Init of Unit Under Test - uut1 : entity work.pc - port map ( - clk => clk, - en_pc => en_pc, - addr_calc => addr_calc, - doJump => doJump, - addr => addr - ); - - -- Process clk_process operating the clock - clk_process : process -- runs only, when changed - begin - clk <= '0'; - wait for clk_period/2; - clk <= '1'; - wait for clk_period/2; - end process; + -- Entity work.pc(pro_count): Init of Unit Under Test + uut1 : entity work.pc + port map ( + clk => clk, + reset => reset, + en_pc => en_pc, + addr_calc => addr_calc, + doJump => doJump, + addr => addr + ); - -- Process stim_proc control device for uut - stim_proc : process -- runs only, when changed - -- Text I/O - variable lineBuffer : line; - begin - - -- wait for the rising edge - wait until rising_edge(clk); - - wait for 10 ns; - - -- Print the top element - write(lineBuffer, string'("Start the simulator")); - writeline(output, lineBuffer); + -- Process clk_process operating the clock + clk_process : process -- runs only, when changed + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; - -- testcases - - -- Case 1: addr_calc - write(lineBuffer, string'("Testing Case 1: ")); - writeline(output, lineBuffer); + -- Process stim_proc control device for uut + stim_proc : process -- runs only, when changed + -- Text I/O + variable lineBuffer : line; + begin - en_pc <= std_logic_vector(to_unsigned(1, 1)); - doJump <= std_logic_vector(to_unsigned(1, 1)); - addr_calc <= std_logic_vector(to_unsigned(30, ram_addr_size)); - wait for 10 ns; + -- wait for the rising edge + wait until rising_edge(clk); - if addr = std_logic_vector(to_unsigned(30, ram_addr_size)) then - write(lineBuffer, string'("Result 1: +")); - writeline(output, lineBuffer); - else - write(lineBuffer, string'("Result 1: -")); - writeline(output, lineBuffer); - end if; - - -- Case 2: count - write(lineBuffer, string'("Testing Case 2: ")); - writeline(output, lineBuffer); + wait for 10 ns; - en_pc <= std_logic_vector(to_unsigned(1, 1)); - doJump <= std_logic_vector(to_unsigned(0, 1)); - addr_calc <= std_logic_vector(to_unsigned(60, ram_addr_size)); - wait for 10 ns; - - --same value from - if addr = std_logic_vector(to_unsigned(31, ram_addr_size)) then - write(lineBuffer, string'("Result 2: +")); - writeline(output, lineBuffer); - else - write(lineBuffer, string'("Result 2: -")); - writeline(output, lineBuffer); - end if; + -- Print the top element + write(lineBuffer, string'("Start the simulator")); + writeline(output, lineBuffer); - -- Case 3: hold - write(lineBuffer, string'("Testing Case 3: ")); - writeline(output, lineBuffer); + -- testcases - en_pc <= std_logic_vector(to_unsigned(0, 1)); - doJump <= std_logic_vector(to_unsigned(0, 1)); - addr_calc <= std_logic_vector(to_unsigned(90, ram_addr_size)); - wait for 10 ns; - - --same value from - if addr = std_logic_vector(to_unsigned(31, ram_addr_size)) then - write(lineBuffer, string'("Result 3: +")); - writeline(output, lineBuffer); - else - write(lineBuffer, string'("Result 3: -")); - writeline(output, lineBuffer); - end if; + -- Case 1: addr_calc + write(lineBuffer, string'("Testing Case 1: ")); + writeline(output, lineBuffer); - -- I'm still waiting - wait; - end process; + en_pc <= std_logic_vector(to_unsigned(1, 1)); + doJump <= std_logic_vector(to_unsigned(1, 1)); + addr_calc <= std_logic_vector(to_unsigned(30, ram_addr_size)); + wait for 10 ns; + + if addr = std_logic_vector(to_unsigned(30, ram_addr_size)) then + write(lineBuffer, string'("Result 1: +")); + writeline(output, lineBuffer); + else + write(lineBuffer, string'("Result 1: -")); + writeline(output, lineBuffer); + end if; + + -- Case 2: count + write(lineBuffer, string'("Testing Case 2: ")); + writeline(output, lineBuffer); + + en_pc <= std_logic_vector(to_unsigned(1, 1)); + doJump <= std_logic_vector(to_unsigned(0, 1)); + addr_calc <= std_logic_vector(to_unsigned(60, ram_addr_size)); + wait for 10 ns; + + --same value from + if addr = std_logic_vector(to_unsigned(31, ram_addr_size)) then + write(lineBuffer, string'("Result 2: +")); + writeline(output, lineBuffer); + else + write(lineBuffer, string'("Result 2: -")); + writeline(output, lineBuffer); + end if; + + -- Case 3: hold + write(lineBuffer, string'("Testing Case 3: ")); + writeline(output, lineBuffer); + + en_pc <= std_logic_vector(to_unsigned(0, 1)); + doJump <= std_logic_vector(to_unsigned(0, 1)); + addr_calc <= std_logic_vector(to_unsigned(90, ram_addr_size)); + wait for 10 ns; + + --same value from + if addr = std_logic_vector(to_unsigned(31, ram_addr_size)) then + write(lineBuffer, string'("Result 3: +")); + writeline(output, lineBuffer); + else + write(lineBuffer, string'("Result 3: -")); + writeline(output, lineBuffer); + end if; + + -- I'm still waiting + wait; + end process; end testing; - - - - + + + + diff --git a/tb/tb_reg.vhd b/tb/tb_reg.vhd index 25d70ae..99c1af9 100644 --- a/tb/tb_reg.vhd +++ b/tb/tb_reg.vhd @@ -12,7 +12,7 @@ library work; use work.riscv_types.all; library std; -use std.textio.all; +use std.textio.all; -- Entity regs_tb: Entity providing testinputs, receiving testoutputs for registerbench entity regs_tb is @@ -20,212 +20,215 @@ end regs_tb; -- Architecture testing of regs_tb: testing read / write operations architecture testing of regs_tb is - -- clock definition - signal clk : std_logic; - constant clk_period : time := 10 ns; + -- clock definition + signal clk : std_logic; + constant clk_period : time := 10 ns; - -- Inputs - signal en_reg_wb_tb : one_bit; - signal data_in_tb : word; - signal wr_idx_tb : reg_idx; - signal r1_idx_tb : reg_idx; - signal r2_idx_tb : reg_idx; - signal write_enable_tb : one_bit; + -- Inputs + signal en_reg_wb_tb : one_bit; + signal data_in_tb : word; + signal wr_idx_tb : reg_idx; + signal r1_idx_tb : reg_idx; + signal r2_idx_tb : reg_idx; + signal write_enable_tb : one_bit; - -- Outputs - signal r1_out_tb : word; - signal r2_out_tb : word; + -- Outputs + signal r1_out_tb : word; + signal r2_out_tb : word; - -- unittest signals - signal random_slv: word; - - --function for random_std_logic_vector - function get_random_slv return std_logic_vector is - - -- random number variablen - variable seed1 : integer := 1; - variable seed2 : integer := 1; - variable r : real; - variable slv : std_logic_vector(wordWidth - 1 downto 0); + -- unittest signals + signal random_slv : word; - begin - for i in slv'range loop - uniform(seed1, seed2, r); - slv(i) := '1' when r > 0.5 else '0'; - end loop; - return slv; - end function; + signal reset : std_logic; + + --function for random_std_logic_vector + function get_random_slv return std_logic_vector is + + -- random number variablen + variable seed1 : integer := 1; + variable seed2 : integer := 1; + variable r : real; + variable slv : std_logic_vector(wordWidth - 1 downto 0); + + begin + for i in slv'range loop + uniform(seed1, seed2, r); + slv(i) := '1' when r > 0.5 else '0'; + end loop; + return slv; + end function; begin - - -- Init of Unit Under Test - uut : entity work.registers(Structure) - port map ( - clk => clk, - en_reg_wb => en_reg_wb_tb, - data_in => data_in_tb, - wr_idx => wr_idx_tb, - r1_idx => r1_idx_tb, - r2_idx => r2_idx_tb, - write_enable => write_enable_tb, - r1_out => r1_out_tb, - r2_out => r2_out_tb - ); - -- Process clk_process operating the clock - clk_process : process -- runs always - begin - clk <= '0'; - wait for clk_period/2; - clk <= '1'; - wait for clk_period/2; - end process; - - -- Stimulating the UUT - -- Process stim_proc control device for - stim_proc : process - -- Text I/O - variable lineBuffer : line; - - begin - - -- wait for the rising edge - wait until rising_edge(clk); - - wait for 5 ns; - - -- Print the top element - write(lineBuffer, string'("Start the simulation: ")); - writeline(output, lineBuffer); + -- Init of Unit Under Test + uut : entity work.registers(Structure) + port map ( + clk => clk, + reset => reset, + en_reg_wb => en_reg_wb_tb, + data_in => data_in_tb, + wr_idx => wr_idx_tb, + r1_idx => r1_idx_tb, + r2_idx => r2_idx_tb, + write_enable => write_enable_tb, + r1_out => r1_out_tb, + r2_out => r2_out_tb + ); - -- set the stimuli here - - -- Case 1: write to x=7 + read x=4 - write(lineBuffer, string'("Testing Case 1: ")); - writeline(output, lineBuffer); + -- Process clk_process operating the clock + clk_process : process -- runs always + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; - write_enable_tb <= std_logic_vector(to_unsigned(1, 1)); - data_in_tb<= std_logic_vector(to_unsigned(7, wordWidth)); - wr_idx_tb <= std_logic_vector(to_unsigned(7, reg_adr_size)); - r1_idx_tb <= std_logic_vector(to_unsigned(4, reg_adr_size)); - r2_idx_tb <= std_logic_vector(to_unsigned(7, reg_adr_size)); - wait for 10 ns; + -- Stimulating the UUT + -- Process stim_proc control device for + stim_proc : process + -- Text I/O + variable lineBuffer : line; - if r1_out_tb = std_logic_vector(to_unsigned(0, wordWidth)) and r2_out_tb = std_logic_vector(to_unsigned(7, wordWidth)) then - write(lineBuffer, string'("Result 1: +")); - writeline(output, lineBuffer); - else - write(lineBuffer, string'("Result 1: -")); - writeline(output, lineBuffer); - end if; + begin - -- Case 2: write to x=27 + read x=0 - write(lineBuffer, string'("Testing Case 2: ")); - writeline(output, lineBuffer); + -- wait for the rising edge + wait until rising_edge(clk); - write_enable_tb <= std_logic_vector(to_unsigned(1, 1)); - data_in_tb<= std_logic_vector(to_unsigned(7, wordWidth)); - wr_idx_tb <= std_logic_vector(to_unsigned(27, reg_adr_size)); - r1_idx_tb <= std_logic_vector(to_unsigned(0, reg_adr_size)); - r2_idx_tb <= std_logic_vector(to_unsigned(27, reg_adr_size)); - wait for 10 ns; + wait for 5 ns; - if r1_out_tb = std_logic_vector(to_unsigned(0, wordWidth)) and r2_out_tb = std_logic_vector(to_unsigned(7, wordWidth)) then - write(lineBuffer, string'("Result 2: +")); - writeline(output, lineBuffer); - else - write(lineBuffer, string'("Result 2: -")); - writeline(output, lineBuffer); - end if; + -- Print the top element + write(lineBuffer, string'("Start the simulation: ")); + writeline(output, lineBuffer); - -- Case 3: write to zero + read from zero x2 - write(lineBuffer, string'("Testing Case 3: ")); - writeline(output, lineBuffer); + -- set the stimuli here - write_enable_tb <= std_logic_vector(to_unsigned(1, 1)); - data_in_tb<= std_logic_vector(to_unsigned(7, wordWidth)); - wr_idx_tb <= std_logic_vector(to_unsigned(0, reg_adr_size)); - r1_idx_tb <= std_logic_vector(to_unsigned(0, reg_adr_size)); - r2_idx_tb <= std_logic_vector(to_unsigned(27, reg_adr_size)); - wait for 10 ns; + -- Case 1: write to x=7 + read x=4 + write(lineBuffer, string'("Testing Case 1: ")); + writeline(output, lineBuffer); - if r1_out_tb = std_logic_vector(to_unsigned(0, wordWidth)) then - write(lineBuffer, string'("Result 3: +")); - writeline(output, lineBuffer); - else - write(lineBuffer, string'("Result 3: -")); - writeline(output, lineBuffer); - end if; + write_enable_tb <= std_logic_vector(to_unsigned(1, 1)); + data_in_tb <= std_logic_vector(to_unsigned(7, wordWidth)); + wr_idx_tb <= std_logic_vector(to_unsigned(7, reg_adr_size)); + r1_idx_tb <= std_logic_vector(to_unsigned(4, reg_adr_size)); + r2_idx_tb <= std_logic_vector(to_unsigned(7, reg_adr_size)); + wait for 10 ns; - -- Case 4: write to 31 + read from 31 - write(lineBuffer, string'("Testing Case 4: ")); - writeline(output, lineBuffer); + if r1_out_tb = std_logic_vector(to_unsigned(0, wordWidth)) and r2_out_tb = std_logic_vector(to_unsigned(7, wordWidth)) then + write(lineBuffer, string'("Result 1: +")); + writeline(output, lineBuffer); + else + write(lineBuffer, string'("Result 1: -")); + writeline(output, lineBuffer); + end if; - write_enable_tb <= std_logic_vector(to_unsigned(1, 1)); - data_in_tb<= std_logic_vector(to_unsigned(7, wordWidth)); - wr_idx_tb <= std_logic_vector(to_unsigned(31, reg_adr_size)); - r1_idx_tb <= std_logic_vector(to_unsigned(31, reg_adr_size)); - r2_idx_tb <= std_logic_vector(to_unsigned(0, reg_adr_size)); - wait for 10 ns; + -- Case 2: write to x=27 + read x=0 + write(lineBuffer, string'("Testing Case 2: ")); + writeline(output, lineBuffer); - if r1_out_tb = std_logic_vector(to_unsigned(7, wordWidth)) then - write(lineBuffer, string'("Result 4: +")); - writeline(output, lineBuffer); - else - write(lineBuffer, string'("Result 4: -")); - writeline(output, lineBuffer); - end if; + write_enable_tb <= std_logic_vector(to_unsigned(1, 1)); + data_in_tb <= std_logic_vector(to_unsigned(7, wordWidth)); + wr_idx_tb <= std_logic_vector(to_unsigned(27, reg_adr_size)); + r1_idx_tb <= std_logic_vector(to_unsigned(0, reg_adr_size)); + r2_idx_tb <= std_logic_vector(to_unsigned(27, reg_adr_size)); + wait for 10 ns; - -- Case 5: read x=7 + read x=18 - write(lineBuffer, string'("Testing Case 5: ")); - writeline(output, lineBuffer); + if r1_out_tb = std_logic_vector(to_unsigned(0, wordWidth)) and r2_out_tb = std_logic_vector(to_unsigned(7, wordWidth)) then + write(lineBuffer, string'("Result 2: +")); + writeline(output, lineBuffer); + else + write(lineBuffer, string'("Result 2: -")); + writeline(output, lineBuffer); + end if; - write_enable_tb <= std_logic_vector(to_unsigned(0, 1)); - data_in_tb<= std_logic_vector(to_unsigned(9, wordWidth)); - wr_idx_tb <= std_logic_vector(to_unsigned(7, reg_adr_size)); - r1_idx_tb <= std_logic_vector(to_unsigned(7, reg_adr_size)); - r2_idx_tb <= std_logic_vector(to_unsigned(18, reg_adr_size)); - wait for 10 ns; - - -- Not allowed to change, last value was 7, new "would" be 9 - if r1_out_tb = std_logic_vector(to_unsigned(7, wordWidth)) then - write(lineBuffer, string'("Result 5: +")); - writeline(output, lineBuffer); - else - write(lineBuffer, string'("Result 5: -")); - writeline(output, lineBuffer); - end if; - - -- Case 6: RANDOM_Test write to 12 + read from 12 - write(lineBuffer, string'("Testing Case 6: ")); - writeline(output, lineBuffer); - - -- get random_logic_vector - random_slv <= get_random_slv; - - wait for 10 ns; - - write_enable_tb <= std_logic_vector(to_unsigned(1, 1)); - data_in_tb <= random_slv; - wr_idx_tb <= std_logic_vector(to_unsigned(12, reg_adr_size)); - r1_idx_tb <= std_logic_vector(to_unsigned(12, reg_adr_size)); - r2_idx_tb <= std_logic_vector(to_unsigned(0, reg_adr_size)); - wait for 10 ns; - - if r1_out_tb = random_slv then - write(lineBuffer, string'("Result 6: +")); - writeline(output, lineBuffer); - else - write(lineBuffer, string'("Result 6: -")); - writeline(output, lineBuffer); - end if; - - -- end simulation - write(lineBuffer, string'("end of simulation")); - writeline(output, lineBuffer); + -- Case 3: write to zero + read from zero x2 + write(lineBuffer, string'("Testing Case 3: ")); + writeline(output, lineBuffer); + + write_enable_tb <= std_logic_vector(to_unsigned(1, 1)); + data_in_tb <= std_logic_vector(to_unsigned(7, wordWidth)); + wr_idx_tb <= std_logic_vector(to_unsigned(0, reg_adr_size)); + r1_idx_tb <= std_logic_vector(to_unsigned(0, reg_adr_size)); + r2_idx_tb <= std_logic_vector(to_unsigned(27, reg_adr_size)); + wait for 10 ns; + + if r1_out_tb = std_logic_vector(to_unsigned(0, wordWidth)) then + write(lineBuffer, string'("Result 3: +")); + writeline(output, lineBuffer); + else + write(lineBuffer, string'("Result 3: -")); + writeline(output, lineBuffer); + end if; + + -- Case 4: write to 31 + read from 31 + write(lineBuffer, string'("Testing Case 4: ")); + writeline(output, lineBuffer); + + write_enable_tb <= std_logic_vector(to_unsigned(1, 1)); + data_in_tb <= std_logic_vector(to_unsigned(7, wordWidth)); + wr_idx_tb <= std_logic_vector(to_unsigned(31, reg_adr_size)); + r1_idx_tb <= std_logic_vector(to_unsigned(31, reg_adr_size)); + r2_idx_tb <= std_logic_vector(to_unsigned(0, reg_adr_size)); + wait for 10 ns; + + if r1_out_tb = std_logic_vector(to_unsigned(7, wordWidth)) then + write(lineBuffer, string'("Result 4: +")); + writeline(output, lineBuffer); + else + write(lineBuffer, string'("Result 4: -")); + writeline(output, lineBuffer); + end if; + + -- Case 5: read x=7 + read x=18 + write(lineBuffer, string'("Testing Case 5: ")); + writeline(output, lineBuffer); + + write_enable_tb <= std_logic_vector(to_unsigned(0, 1)); + data_in_tb <= std_logic_vector(to_unsigned(9, wordWidth)); + wr_idx_tb <= std_logic_vector(to_unsigned(7, reg_adr_size)); + r1_idx_tb <= std_logic_vector(to_unsigned(7, reg_adr_size)); + r2_idx_tb <= std_logic_vector(to_unsigned(18, reg_adr_size)); + wait for 10 ns; + + -- Not allowed to change, last value was 7, new "would" be 9 + if r1_out_tb = std_logic_vector(to_unsigned(7, wordWidth)) then + write(lineBuffer, string'("Result 5: +")); + writeline(output, lineBuffer); + else + write(lineBuffer, string'("Result 5: -")); + writeline(output, lineBuffer); + end if; + + -- Case 6: RANDOM_Test write to 12 + read from 12 + write(lineBuffer, string'("Testing Case 6: ")); + writeline(output, lineBuffer); + + -- get random_logic_vector + random_slv <= get_random_slv; + + wait for 10 ns; + + write_enable_tb <= std_logic_vector(to_unsigned(1, 1)); + data_in_tb <= random_slv; + wr_idx_tb <= std_logic_vector(to_unsigned(12, reg_adr_size)); + r1_idx_tb <= std_logic_vector(to_unsigned(12, reg_adr_size)); + r2_idx_tb <= std_logic_vector(to_unsigned(0, reg_adr_size)); + wait for 10 ns; + + if r1_out_tb = random_slv then + write(lineBuffer, string'("Result 6: +")); + writeline(output, lineBuffer); + else + write(lineBuffer, string'("Result 6: -")); + writeline(output, lineBuffer); + end if; + + -- end simulation + write(lineBuffer, string'("end of simulation")); + writeline(output, lineBuffer); + + -- I'm still waiting + wait; + end process; - -- I'm still waiting - wait; - end process; - end testing;