commit d339d53c39d82e853ff7fb40cc4b7242bd874813 Author: yannickreiss Date: Mon Jan 29 19:13:01 2024 +0100 init diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..67657bf --- /dev/null +++ b/.gitignore @@ -0,0 +1,5 @@ +*.o +*.ghw +*.cf +xvhdl* +Vivado* diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..478f80f --- /dev/null +++ b/Makefile @@ -0,0 +1,76 @@ +# Makefile for the different parts of the RISC-V COntroller +# Project by +# Yannick Reiß +# Carl Ries +# Alexander Graf + +# Variable section +PARTS = ram regs alu decoder pc cpu +CHDL = ghdl +FLAGS = --std=08 +REGSSRC = src/riscv_types.vhd src/registers.vhd tb/tb_reg.vhd +ALUSRC = src/riscv_types.vhd src/alu.vhd tb/tb_alu.vhd +RAMSRC = src/riscv_types.vhd src/ram_block.vhd src/imem.vhd src/ram_entity_only.vhd tb/tb_ram.vhd +PCSRC = src/riscv_types.vhd src/pc.vhd tb/tb_pc.vhd +DECSRC = src/riscv_types.vhd src/decoder.vhd tb/tb_decoder.vhd +CPUSRC = src/riscv_types.vhd src/ram_block.vhd src/branch.vhd src/imem.vhd src/ram_entity_only.vhd src/registers.vhd src/alu.vhd src/pc.vhd src/decoder.vhd src/imm.vhd src/cpu.vhd tb/tb_cpu.vhd +ENTITY = regs_tb +ALUENTITY = alu_tb +PCENTITY = pc_tb +STOP = 9000ns +TBENCH = alu_tb regs_tb + +# Build all +all: $(PARTS) + +# ram testbench +ram: $(RAMSRC) + $(CHDL) -a $(FLAGS) $(RAMSRC) + $(CHDL) -e $(FLAGS) ram_tb + $(CHDL) -r $(FLAGS) ram_tb --wave=ram_tb.ghw --stop-time=$(STOP) + +# registerbank testbench +regs: $(REGSSRC) + $(CHDL) -a $(FLAGS) $(REGSSRC) + $(CHDL) -e $(FLAGS) $(ENTITY) + $(CHDL) -r $(FLAGS) $(ENTITY) --wave=$(ENTITY).ghw --stop-time=$(STOP) + +# alu testbench +alu : $(ALUSRC) + $(CHDL) -a $(FLAGS) $(ALUSRC) + $(CHDL) -e $(FLAGS) $(ALUENTITY) + $(CHDL) -r $(FLAGS) $(ALUENTITY) --wave=$(ALUENTITY).ghw --stop-time=$(STOP) + +# pc testbench +pc : $(PCSRC) + $(CHDL) -a $(FLAGS) $(PCSRC) + $(CHDL) -e $(FLAGS) $(PCENTITY) + $(CHDL) -r $(FLAGS) $(PCENTITY) --wave=$(PCENTITY).ghw --stop-time=$(STOP) + +# decoder compilecheck +decoder: $(DECSRC) + $(CHDL) -a $(FLAGS) $(DECSRC) + $(CHDL) -e $(FLAGS) decoder_tb + $(CHDL) -r $(FLAGS) decoder_tb --wave=decode.ghw --stop-time=600ns + +# cpu compilecheck +cpu: $(CPUSRC) + $(CHDL) -a $(FLAGS) $(CPUSRC) + $(CHDL) -e $(FLAGS) cpu_tb + $(CHDL) -r $(FLAGS) cpu_tb --wave=cpu.ghw --stop-time=60000ns + +# imm compilecheck +imm: src/imm.vhd + $(CHDL) -a $(FLAGS) src/riscv_types.vhd src/imm.vhd tb/tb_imm.vhd + $(CHDL) -e $(FLAGS) imm_tb + $(CHDL) -r $(FLAGS) imm_tb --wave=imm.ghw --stop-time=600ns + +# project rules +clean: + find . -name '*.o' -exec rm -r {} \; + find . -name '*.cf' -exec rm -r {} \; + find . -name '*.ghw' -exec rm -r {} \; + find . -name '*_tb' -exec rm -r {} \; + rm alu_tb regs_tb decoder_tb ram_tb pc_tb + +.PHONY: ram all regs cpu clean diff --git a/README.md b/README.md new file mode 100644 index 0000000..7a41362 --- /dev/null +++ b/README.md @@ -0,0 +1,74 @@ +# RISC-V Prozessor +## Requirements +- make +- ghdl +- gtkwave (optional) + +--- + +## Build Instructions +To analyze, elaborate and run all entity testbenches use +```bash +make all +``` + +To build just one specific testbench use +```bash +make +``` +with entity being one of *ram*, *regs*, *alu*, *imm*, *decoder* and *cpu* at the moment. + +Make sure to clean the project by using the command +```bash +make clean +``` +before commit or push to the repository. + +--- + +## Config / structure +Ram size: 4096b => 4kb divided in 1kb Instruction, 3kb Data +Instruction set: 32i Base Instructions (currently R | I | S implemented) + +## Git +### Branches +Open new Branch when +- you start working on more than one file or +- you do more than minor changes to existing code +- you plan on improving already finished parts +- you want to make changes for testing + +### Commits +- Commit after every major change +- If creating a new file do +```bash +git commit +``` +for only this file +- Give a brief and precice description of your changes +- Use ERROR/WARNING/BUG to indicate a problem in your commit +- Make sure to only commit important files + +### Merges +- Only merge, if your branch is worked out +- Don't merge branches with errors, or bugs, unless we merge all branches together +- If filestructure was changed, do a rebase instead + +--- + +## Code +### Comments +- Comment every entity/architecture/process/etc. +- Comments should be less than one sentence +- No comments for single statements + +### Naming and Style +- avoid meaningless names for signals, ports, variables +- use 2 spaces or tabsize 2 intendation +- name every process, entity, ... +- FORMAT FILE WITH EMACS (C-c + C-b) + +### Programming conventions +- reduce the use of programming control structures as far as possible +- if possible use switch case instead of if +- use if statements instead of index access to vectors (avoiding latches) diff --git a/constrainits.xdc b/constrainits.xdc new file mode 100644 index 0000000..2e4e7c6 --- /dev/null +++ b/constrainits.xdc @@ -0,0 +1,721 @@ +## This file is a general .xdc for the Nexys4 rev B board +## To use it in a project: +## - uncomment the lines corresponding to used pins +## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project + +## Clock signal +##Bank = 35, Pin name = IO_L12P_T1_MRCC_35, Sch name = CLK100MHZ +set_property PACKAGE_PIN E3 [get_ports clk] + set_property IOSTANDARD LVCMOS33 [get_ports clk] + create_clock -add -name clk -period 350.00 -waveform {0 5} [get_ports clk] + +## Switches +##Bank = 34, Pin name = IO_L21P_T3_DQS_34, Sch name = SW0 +# set_property PACKAGE_PIN U9 [get_ports {RESET}] +# set_property IOSTANDARD LVCMOS33 [get_ports {RESET}] +##Bank = 34, Pin name = IO_25_34, Sch name = SW1 +#set_property PACKAGE_PIN U8 [get_ports {sw[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}] +##Bank = 34, Pin name = IO_L23P_T3_34, Sch name = SW2 +#set_property PACKAGE_PIN R7 [get_ports {sw[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}] +##Bank = 34, Pin name = IO_L19P_T3_34, Sch name = SW3 +#set_property PACKAGE_PIN R6 [get_ports {sw[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}] +##Bank = 34, Pin name = IO_L19N_T3_VREF_34, Sch name = SW4 +#set_property PACKAGE_PIN R5 [get_ports {sw[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}] +##Bank = 34, Pin name = IO_L20P_T3_34, Sch name = SW5 +#set_property PACKAGE_PIN V7 [get_ports {sw[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}] +##Bank = 34, Pin name = IO_L20N_T3_34, Sch name = SW6 +#set_property PACKAGE_PIN V6 [get_ports {sw[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}] +##Bank = 34, Pin name = IO_L10P_T1_34, Sch name = SW7 +#set_property PACKAGE_PIN V5 [get_ports {sw[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}] +##Bank = 34, Pin name = IO_L8P_T1-34, Sch name = SW8 +#set_property PACKAGE_PIN U4 [get_ports {sw[8]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}] +##Bank = 34, Pin name = IO_L9N_T1_DQS_34, Sch name = SW9 +#set_property PACKAGE_PIN V2 [get_ports {sw[9]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}] +##Bank = 34, Pin name = IO_L9P_T1_DQS_34, Sch name = SW10 +#set_property PACKAGE_PIN U2 [get_ports {sw[10]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}] +##Bank = 34, Pin name = IO_L11N_T1_MRCC_34, Sch name = SW11 +#set_property PACKAGE_PIN T3 [get_ports {sw[11]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}] +##Bank = 34, Pin name = IO_L17N_T2_34, Sch name = SW12 +#set_property PACKAGE_PIN T1 [get_ports {sw[12]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}] +##Bank = 34, Pin name = IO_L11P_T1_SRCC_34, Sch name = SW13 +#set_property PACKAGE_PIN R3 [get_ports {sw[13]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}] +##Bank = 34, Pin name = IO_L14N_T2_SRCC_34, Sch name = SW14 +#set_property PACKAGE_PIN P3 [get_ports {sw[14]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}] +##Bank = 34, Pin name = IO_L14P_T2_SRCC_34, Sch name = SW15 +#set_property PACKAGE_PIN P4 [get_ports {sw[15]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}] + + + +## LEDs +##Bank = 34, Pin name = IO_L24N_T3_34, Sch name = LED0 +set_property PACKAGE_PIN T8 [get_ports {led[0]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}] +#Bank = 34, Pin name = IO_L21N_T3_DQS_34, Sch name = LED1 +set_property PACKAGE_PIN V9 [get_ports {led[1]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}] +#Bank = 34, Pin name = IO_L24P_T3_34, Sch name = LED2 + set_property PACKAGE_PIN R8 [get_ports {led[2]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}] +#Bank = 34, Pin name = IO_L23N_T3_34, Sch name = LED3 + set_property PACKAGE_PIN T6 [get_ports {led[3]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}] +#Bank = 34, Pin name = IO_L12P_T1_MRCC_34, Sch name = LED4 +set_property PACKAGE_PIN T5 [get_ports {led[4]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}] +#Bank = 34, Pin name = IO_L12N_T1_MRCC_34, Sch name = LED5 +set_property PACKAGE_PIN T4 [get_ports {led[5]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}] +#Bank = 34, Pin name = IO_L22P_T3_34, Sch name = LED6 +set_property PACKAGE_PIN U7 [get_ports {led[6]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}] +#Bank = 34, Pin name = IO_L22N_T3_34, Sch name = LED7 +set_property PACKAGE_PIN U6 [get_ports {led[7]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}] +##Bank = 34, Pin name = IO_L10N_T1_34, Sch name = LED8 +set_property PACKAGE_PIN V4 [get_ports {led[8]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}] +##Bank = 34, Pin name = IO_L8N_T1_34, Sch name = LED9 +set_property PACKAGE_PIN U3 [get_ports {led[9]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}] +##Bank = 34, Pin name = IO_L7N_T1_34, Sch name = LED10 +set_property PACKAGE_PIN V1 [get_ports {led[10]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}] +##Bank = 34, Pin name = IO_L17P_T2_34, Sch name = LED11 +set_property PACKAGE_PIN R1 [get_ports {led[11]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}] +##Bank = 34, Pin name = IO_L13N_T2_MRCC_34, Sch name = LED12 +set_property PACKAGE_PIN P5 [get_ports {led[12]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}] +##Bank = 34, Pin name = IO_L7P_T1_34, Sch name = LED13 +set_property PACKAGE_PIN U1 [get_ports {led[13]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}] +##Bank = 34, Pin name = IO_L15N_T2_DQS_34, Sch name = LED14 +set_property PACKAGE_PIN R2 [get_ports {led[14]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}] +##Bank = 34, Pin name = IO_L15P_T2_DQS_34, Sch name = LED15 +set_property PACKAGE_PIN P2 [get_ports {led[15]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}] + +##Bank = 34, Pin name = IO_L5P_T0_34, Sch name = LED16_R +set_property PACKAGE_PIN K5 [get_ports {RGB1[0]}] + set_property IOSTANDARD LVCMOS33 [get_ports {RGB1[0]}] +##Bank = 15, Pin name = IO_L5P_T0_AD9P_15, Sch name = LED16_G +set_property PACKAGE_PIN F13 [get_ports {RGB1[1]}] + set_property IOSTANDARD LVCMOS33 [get_ports {RGB1[1]}] +##Bank = 35, Pin name = IO_L19N_T3_VREF_35, Sch name = LED16_B +set_property PACKAGE_PIN F6 [get_ports {RGB1[2]}] + set_property IOSTANDARD LVCMOS33 [get_ports {RGB1[2]}] +##Bank = 34, Pin name = IO_0_34, Sch name = LED17_R +set_property PACKAGE_PIN K6 [get_ports {RGB2[0]}] + set_property IOSTANDARD LVCMOS33 [get_ports {RGB2[0]}] +##Bank = 35, Pin name = IO_24P_T3_35, Sch name = LED17_G +set_property PACKAGE_PIN H6 [get_ports {RGB2[1]}] + set_property IOSTANDARD LVCMOS33 [get_ports {RGB2[1]}] +##Bank = CONFIG, Pin name = IO_L3N_T0_DQS_EMCCLK_14, Sch name = LED17_B +set_property PACKAGE_PIN L16 [get_ports {RGB2[2]}] + set_property IOSTANDARD LVCMOS33 [get_ports {RGB2[2]}] + + + +##7 segment display +##Bank = 34, Pin name = IO_L2N_T0_34, Sch name = CA +#set_property PACKAGE_PIN L3 [get_ports {seg[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}] +##Bank = 34, Pin name = IO_L3N_T0_DQS_34, Sch name = CB +#set_property PACKAGE_PIN N1 [get_ports {seg[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}] +##Bank = 34, Pin name = IO_L6N_T0_VREF_34, Sch name = CC +#set_property PACKAGE_PIN L5 [get_ports {seg[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}] +##Bank = 34, Pin name = IO_L5N_T0_34, Sch name = CD +#set_property PACKAGE_PIN L4 [get_ports {seg[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}] +##Bank = 34, Pin name = IO_L2P_T0_34, Sch name = CE +#set_property PACKAGE_PIN K3 [get_ports {seg[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}] +##Bank = 34, Pin name = IO_L4N_T0_34, Sch name = CF +#set_property PACKAGE_PIN M2 [get_ports {seg[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}] +##Bank = 34, Pin name = IO_L6P_T0_34, Sch name = CG +#set_property PACKAGE_PIN L6 [get_ports {seg[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}] + +##Bank = 34, Pin name = IO_L16P_T2_34, Sch name = DP +#set_property PACKAGE_PIN M4 [get_ports dp] + #set_property IOSTANDARD LVCMOS33 [get_ports dp] + +##Bank = 34, Pin name = IO_L18N_T2_34, Sch name = AN0 +#set_property PACKAGE_PIN N6 [get_ports {an[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}] +##Bank = 34, Pin name = IO_L18P_T2_34, Sch name = AN1 +#set_property PACKAGE_PIN M6 [get_ports {an[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}] +##Bank = 34, Pin name = IO_L4P_T0_34, Sch name = AN2 +#set_property PACKAGE_PIN M3 [get_ports {an[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}] +##Bank = 34, Pin name = IO_L13_T2_MRCC_34, Sch name = AN3 +#set_property PACKAGE_PIN N5 [get_ports {an[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}] +##Bank = 34, Pin name = IO_L3P_T0_DQS_34, Sch name = AN4 +#set_property PACKAGE_PIN N2 [get_ports {an[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {an[4]}] +##Bank = 34, Pin name = IO_L16N_T2_34, Sch name = AN5 +#set_property PACKAGE_PIN N4 [get_ports {an[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {an[5]}] +##Bank = 34, Pin name = IO_L1P_T0_34, Sch name = AN6 +#set_property PACKAGE_PIN L1 [get_ports {an[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {an[6]}] +##Bank = 34, Pin name = IO_L1N_T034, Sch name = AN7 +#set_property PACKAGE_PIN M1 [get_ports {an[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {an[7]}] + + + +##Buttons +##Bank = 15, Pin name = IO_L3P_T0_DQS_AD1P_15, Sch name = CPU_RESET +#set_property PACKAGE_PIN C12 [get_ports btnCpuReset] + #set_property IOSTANDARD LVCMOS33 [get_ports btnCpuReset] +##Bank = 15, Pin name = IO_L11N_T1_SRCC_15, Sch name = BTNC +#set_property PACKAGE_PIN E16 [get_ports clk] +# set_property IOSTANDARD LVCMOS33 [get_ports clk] +##Bank = 15, Pin name = IO_L14P_T2_SRCC_15, Sch name = BTNU +#set_property PACKAGE_PIN F15 [get_ports btnU] + #set_property IOSTANDARD LVCMOS33 [get_ports btnU] +##Bank = CONFIG, Pin name = IO_L15N_T2_DQS_DOUT_CSO_B_14, Sch name = BTNL +#set_property PACKAGE_PIN T16 [get_ports btnL] + #set_property IOSTANDARD LVCMOS33 [get_ports btnL] +##Bank = 14, Pin name = IO_25_14, Sch name = BTNR +#set_property PACKAGE_PIN R10 [get_ports btnR] + #set_property IOSTANDARD LVCMOS33 [get_ports btnR] +##Bank = 14, Pin name = IO_L21P_T3_DQS_14, Sch name = BTND +#set_property PACKAGE_PIN V10 [get_ports btnD] + #set_property IOSTANDARD LVCMOS33 [get_ports btnD] + + + +##Pmod Header JA +##Bank = 15, Pin name = IO_L1N_T0_AD0N_15, Sch name = JA1 +#set_property PACKAGE_PIN B13 [get_ports {JA[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}] +##Bank = 15, Pin name = IO_L5N_T0_AD9N_15, Sch name = JA2 +#set_property PACKAGE_PIN F14 [get_ports {JA[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}] +##Bank = 15, Pin name = IO_L16N_T2_A27_15, Sch name = JA3 +#set_property PACKAGE_PIN D17 [get_ports {JA[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}] +##Bank = 15, Pin name = IO_L16P_T2_A28_15, Sch name = JA4 +#set_property PACKAGE_PIN E17 [get_ports {JA[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}] +##Bank = 15, Pin name = IO_0_15, Sch name = JA7 +#set_property PACKAGE_PIN G13 [get_ports {JA[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}] +##Bank = 15, Pin name = IO_L20N_T3_A19_15, Sch name = JA8 +#set_property PACKAGE_PIN C17 [get_ports {JA[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}] +##Bank = 15, Pin name = IO_L21N_T3_A17_15, Sch name = JA9 +#set_property PACKAGE_PIN D18 [get_ports {JA[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}] +##Bank = 15, Pin name = IO_L21P_T3_DQS_15, Sch name = JA10 +#set_property PACKAGE_PIN E18 [get_ports {JA[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}] + + + +##Pmod Header JB +##Bank = 15, Pin name = IO_L15N_T2_DQS_ADV_B_15, Sch name = JB1 +#set_property PACKAGE_PIN G14 [get_ports {JB[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}] +##Bank = 14, Pin name = IO_L13P_T2_MRCC_14, Sch name = JB2 +#set_property PACKAGE_PIN P15 [get_ports {JB[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}] +##Bank = 14, Pin name = IO_L21N_T3_DQS_A06_D22_14, Sch name = JB3 +#set_property PACKAGE_PIN V11 [get_ports {JB[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}] +##Bank = CONFIG, Pin name = IO_L16P_T2_CSI_B_14, Sch name = JB4 +#set_property PACKAGE_PIN V15 [get_ports {JB[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}] +##Bank = 15, Pin name = IO_25_15, Sch name = JB7 +#set_property PACKAGE_PIN K16 [get_ports {JB[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}] +##Bank = CONFIG, Pin name = IO_L15P_T2_DQS_RWR_B_14, Sch name = JB8 +#set_property PACKAGE_PIN R16 [get_ports {JB[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}] +##Bank = 14, Pin name = IO_L24P_T3_A01_D17_14, Sch name = JB9 +#set_property PACKAGE_PIN T9 [get_ports {JB[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}] +##Bank = 14, Pin name = IO_L19N_T3_A09_D25_VREF_14, Sch name = JB10 +#set_property PACKAGE_PIN U11 [get_ports {JB[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}] + + + +##Pmod Header JC +##Bank = 35, Pin name = IO_L23P_T3_35, Sch name = JC1 +#set_property PACKAGE_PIN K2 [get_ports {JC[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}] +##Bank = 35, Pin name = IO_L6P_T0_35, Sch name = JC2 +#set_property PACKAGE_PIN E7 [get_ports {JC[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}] +##Bank = 35, Pin name = IO_L22P_T3_35, Sch name = JC3 +#set_property PACKAGE_PIN J3 [get_ports {JC[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}] +##Bank = 35, Pin name = IO_L21P_T3_DQS_35, Sch name = JC4 +#set_property PACKAGE_PIN J4 [get_ports {JC[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}] +##Bank = 35, Pin name = IO_L23N_T3_35, Sch name = JC7 +#set_property PACKAGE_PIN K1 [get_ports {JC[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}] +##Bank = 35, Pin name = IO_L5P_T0_AD13P_35, Sch name = JC8 +#set_property PACKAGE_PIN E6 [get_ports {JC[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}] +##Bank = 35, Pin name = IO_L22N_T3_35, Sch name = JC9 +#set_property PACKAGE_PIN J2 [get_ports {JC[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}] +##Bank = 35, Pin name = IO_L19P_T3_35, Sch name = JC10 +#set_property PACKAGE_PIN G6 [get_ports {JC[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}] + + + +##Pmod Header JD +##Bank = 35, Pin name = IO_L21N_T2_DQS_35, Sch name = JD1 +#set_property PACKAGE_PIN H4 [get_ports {JD[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JD[0]}] +##Bank = 35, Pin name = IO_L17P_T2_35, Sch name = JD2 +#set_property PACKAGE_PIN H1 [get_ports {JD[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JD[1]}] +##Bank = 35, Pin name = IO_L17N_T2_35, Sch name = JD3 +#set_property PACKAGE_PIN G1 [get_ports {JD[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JD[2]}] +##Bank = 35, Pin name = IO_L20N_T3_35, Sch name = JD4 +#set_property PACKAGE_PIN G3 [get_ports {JD[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JD[3]}] +##Bank = 35, Pin name = IO_L15P_T2_DQS_35, Sch name = JD7 +#set_property PACKAGE_PIN H2 [get_ports {JD[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JD[4]}] +##Bank = 35, Pin name = IO_L20P_T3_35, Sch name = JD8 +#set_property PACKAGE_PIN G4 [get_ports {JD[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JD[5]}] +##Bank = 35, Pin name = IO_L15N_T2_DQS_35, Sch name = JD9 +#set_property PACKAGE_PIN G2 [get_ports {JD[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JD[6]}] +##Bank = 35, Pin name = IO_L13N_T2_MRCC_35, Sch name = JD10 +#set_property PACKAGE_PIN F3 [get_ports {JD[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JD[7]}] + + + +##Pmod Header JXADC +##Bank = 15, Pin name = IO_L9P_T1_DQS_AD3P_15, Sch name = XADC1_P -> XA1_P +#set_property PACKAGE_PIN A13 [get_ports {JXADC[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}] +##Bank = 15, Pin name = IO_L8P_T1_AD10P_15, Sch name = XADC2_P -> XA2_P +#set_property PACKAGE_PIN A15 [get_ports {JXADC[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}] +##Bank = 15, Pin name = IO_L7P_T1_AD2P_15, Sch name = XADC3_P -> XA3_P +#set_property PACKAGE_PIN B16 [get_ports {JXADC[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}] +##Bank = 15, Pin name = IO_L10P_T1_AD11P_15, Sch name = XADC4_P -> XA4_P +#set_property PACKAGE_PIN B18 [get_ports {JXADC[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}] +##Bank = 15, Pin name = IO_L9N_T1_DQS_AD3N_15, Sch name = XADC1_N -> XA1_N +#set_property PACKAGE_PIN A14 [get_ports {JXADC[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}] +##Bank = 15, Pin name = IO_L8N_T1_AD10N_15, Sch name = XADC2_N -> XA2_N +#set_property PACKAGE_PIN A16 [get_ports {JXADC[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}] +##Bank = 15, Pin name = IO_L7N_T1_AD2N_15, Sch name = XADC3_N -> XA3_N +#set_property PACKAGE_PIN B17 [get_ports {JXADC[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}] +##Bank = 15, Pin name = IO_L10N_T1_AD11N_15, Sch name = XADC4_N -> XA4_N +#set_property PACKAGE_PIN A18 [get_ports {JXADC[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}] + + + +##VGA Connector +##Bank = 35, Pin name = IO_L8N_T1_AD14N_35, Sch name = VGA_R0 +#set_property PACKAGE_PIN A3 [get_ports {vgaRed[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}] +##Bank = 35, Pin name = IO_L7N_T1_AD6N_35, Sch name = VGA_R1 +#set_property PACKAGE_PIN B4 [get_ports {vgaRed[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}] +##Bank = 35, Pin name = IO_L1N_T0_AD4N_35, Sch name = VGA_R2 +#set_property PACKAGE_PIN C5 [get_ports {vgaRed[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}] +##Bank = 35, Pin name = IO_L8P_T1_AD14P_35, Sch name = VGA_R3 +#set_property PACKAGE_PIN A4 [get_ports {vgaRed[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}] +##Bank = 35, Pin name = IO_L2P_T0_AD12P_35, Sch name = VGA_B0 +#set_property PACKAGE_PIN B7 [get_ports {vgaBlue[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}] +##Bank = 35, Pin name = IO_L4N_T0_35, Sch name = VGA_B1 +#set_property PACKAGE_PIN C7 [get_ports {vgaBlue[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}] +##Bank = 35, Pin name = IO_L6N_T0_VREF_35, Sch name = VGA_B2 +#set_property PACKAGE_PIN D7 [get_ports {vgaBlue[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}] +##Bank = 35, Pin name = IO_L4P_T0_35, Sch name = VGA_B3 +#set_property PACKAGE_PIN D8 [get_ports {vgaBlue[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}] +##Bank = 35, Pin name = IO_L1P_T0_AD4P_35, Sch name = VGA_G0 +#set_property PACKAGE_PIN C6 [get_ports {vgaGreen[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}] +##Bank = 35, Pin name = IO_L3N_T0_DQS_AD5N_35, Sch name = VGA_G1 +#set_property PACKAGE_PIN A5 [get_ports {vgaGreen[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}] +##Bank = 35, Pin name = IO_L2N_T0_AD12N_35, Sch name = VGA_G2 +#set_property PACKAGE_PIN B6 [get_ports {vgaGreen[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}] +##Bank = 35, Pin name = IO_L3P_T0_DQS_AD5P_35, Sch name = VGA_G3 +#set_property PACKAGE_PIN A6 [get_ports {vgaGreen[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}] +##Bank = 15, Pin name = IO_L4P_T0_15, Sch name = VGA_HS +#set_property PACKAGE_PIN B11 [get_ports Hsync] + #set_property IOSTANDARD LVCMOS33 [get_ports Hsync] +##Bank = 15, Pin name = IO_L3N_T0_DQS_AD1N_15, Sch name = VGA_VS +#set_property PACKAGE_PIN B12 [get_ports Vsync] + #set_property IOSTANDARD LVCMOS33 [get_ports Vsync] + + + +##Micro SD Connector +##Bank = 35, Pin name = IO_L14P_T2_SRCC_35, Sch name = SD_RESET +#set_property PACKAGE_PIN E2 [get_ports sdReset] + #set_property IOSTANDARD LVCMOS33 [get_ports sdReset] +##Bank = 35, Pin name = IO_L9N_T1_DQS_AD7N_35, Sch name = SD_CD +#set_property PACKAGE_PIN A1 [get_ports sdCD] + #set_property IOSTANDARD LVCMOS33 [get_ports sdCD] +##Bank = 35, Pin name = IO_L9P_T1_DQS_AD7P_35, Sch name = SD_SCK +#set_property PACKAGE_PIN B1 [get_ports sdSCK] + #set_property IOSTANDARD LVCMOS33 [get_ports sdSCK] +##Bank = 35, Pin name = IO_L16N_T2_35, Sch name = SD_CMD +#set_property PACKAGE_PIN C1 [get_ports sdCmd] + #set_property IOSTANDARD LVCMOS33 [get_ports sdCmd] +##Bank = 35, Pin name = IO_L16P_T2_35, Sch name = SD_DAT0 +#set_property PACKAGE_PIN C2 [get_ports {sdData[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sdData[0]}] +##Bank = 35, Pin name = IO_L18N_T2_35, Sch name = SD_DAT1 +#set_property PACKAGE_PIN E1 [get_ports {sdData[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sdData[1]}] +##Bank = 35, Pin name = IO_L18P_T2_35, Sch name = SD_DAT2 +#set_property PACKAGE_PIN F1 [get_ports {sdData[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sdData[2]}] +##Bank = 35, Pin name = IO_L14N_T2_SRCC_35, Sch name = SD_DAT3 +#set_property PACKAGE_PIN D2 [get_ports {sdData[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sdData[3]}] + + + +##Accelerometer +##Bank = 15, Pin name = IO_L6N_T0_VREF_15, Sch name = ACL_MISO +#set_property PACKAGE_PIN D13 [get_ports MISO] +# set_property IOSTANDARD LVCMOS33 [get_ports MISO] +#Bank = 15, Pin name = IO_L2N_T0_AD8N_15, Sch name = ACL_MOSI +#set_property PACKAGE_PIN B14 [get_ports MOSI] +# set_property IOSTANDARD LVCMOS33 [get_ports MOSI] +#Bank = 15, Pin name = IO_L12P_T1_MRCC_15, Sch name = ACL_SCLK +#set_property PACKAGE_PIN D15 [get_ports SCLK] +# set_property IOSTANDARD LVCMOS33 [get_ports SCLK] +#Bank = 15, Pin name = IO_L12N_T1_MRCC_15, Sch name = ACL_CSN +#set_property PACKAGE_PIN C15 [get_ports SS] +# set_property IOSTANDARD LVCMOS33 [get_ports SS] +##Bank = 15, Pin name = IO_L20P_T3_A20_15, Sch name = ACL_INT1 +#set_property PACKAGE_PIN C16 [get_ports aclInt1] + #set_property IOSTANDARD LVCMOS33 [get_ports aclInt1] +##Bank = 15, Pin name = IO_L11P_T1_SRCC_15, Sch name = ACL_INT2 +#set_property PACKAGE_PIN E15 [get_ports aclInt2] + #set_property IOSTANDARD LVCMOS33 [get_ports aclInt2] + + + +##Temperature Sensor +##Bank = 15, Pin name = IO_L14N_T2_SRCC_15, Sch name = TMP_SCL +#set_property PACKAGE_PIN F16 [get_ports tmpSCL] + #set_property IOSTANDARD LVCMOS33 [get_ports tmpSCL] +##Bank = 15, Pin name = IO_L13N_T2_MRCC_15, Sch name = TMP_SDA +#set_property PACKAGE_PIN G16 [get_ports tmpSDA] + #set_property IOSTANDARD LVCMOS33 [get_ports tmpSDA] +##Bank = 15, Pin name = IO_L1P_T0_AD0P_15, Sch name = TMP_INT +#set_property PACKAGE_PIN D14 [get_ports tmpInt] + #set_property IOSTANDARD LVCMOS33 [get_ports tmpInt] +##Bank = 15, Pin name = IO_L1N_T0_AD0N_15, Sch name = TMP_CT +#set_property PACKAGE_PIN C14 [get_ports tmpCT] + #set_property IOSTANDARD LVCMOS33 [get_ports tmpCT] + + + +##Omnidirectional Microphone +##Bank = 35, Pin name = IO_25_35, Sch name = M_CLK +#set_property PACKAGE_PIN J5 [get_ports micClk] + #set_property IOSTANDARD LVCMOS33 [get_ports micClk] +##Bank = 35, Pin name = IO_L24N_T3_35, Sch name = M_DATA +#set_property PACKAGE_PIN H5 [get_ports micData] + #set_property IOSTANDARD LVCMOS33 [get_ports micData] +##Bank = 35, Pin name = IO_0_35, Sch name = M_LRSEL +#set_property PACKAGE_PIN F5 [get_ports micLRSel] + #set_property IOSTANDARD LVCMOS33 [get_ports micLRSel] + + + +##PWM Audio Amplifier +##Bank = 15, Pin name = IO_L4N_T0_15, Sch name = AUD_PWM +#set_property PACKAGE_PIN A11 [get_ports ampPWM] + #set_property IOSTANDARD LVCMOS33 [get_ports ampPWM] +##Bank = 15, Pin name = IO_L6P_T0_15, Sch name = AUD_SD +#set_property PACKAGE_PIN D12 [get_ports ampSD] + #set_property IOSTANDARD LVCMOS33 [get_ports ampSD] + + +##USB-RS232 Interface +##Bank = 35, Pin name = IO_L7P_T1_AD6P_35, Sch name = UART_TXD_IN +#set_property PACKAGE_PIN C4 [get_ports RsRx] + #set_property IOSTANDARD LVCMOS33 [get_ports RsRx] +##Bank = 35, Pin name = IO_L11N_T1_SRCC_35, Sch name = UART_RXD_OUT +#set_property PACKAGE_PIN D4 [get_ports RsTx] + #set_property IOSTANDARD LVCMOS33 [get_ports RsTx] +##Bank = 35, Pin name = IO_L12N_T1_MRCC_35, Sch name = UART_CTS +#set_property PACKAGE_PIN D3 [get_ports RsCts] + #set_property IOSTANDARD LVCMOS33 [get_ports RsCts] +##Bank = 35, Pin name = IO_L5N_T0_AD13N_35, Sch name = UART_RTS +#set_property PACKAGE_PIN E5 [get_ports RsRts] + #set_property IOSTANDARD LVCMOS33 [get_ports RsRts] + + + +##USB HID (PS/2) +##Bank = 35, Pin name = IO_L13P_T2_MRCC_35, Sch name = PS2_CLK +#set_property PACKAGE_PIN F4 [get_ports PS2Clk] + #set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk] + #set_property PULLUP true [get_ports PS2Clk] +##Bank = 35, Pin name = IO_L10N_T1_AD15N_35, Sch name = PS2_DATA +#set_property PACKAGE_PIN B2 [get_ports PS2Data] + #set_property IOSTANDARD LVCMOS33 [get_ports PS2Data] + #set_property PULLUP true [get_ports PS2Data] + + + +##SMSC Ethernet PHY +##Bank = 16, Pin name = IO_L11P_T1_SRCC_16, Sch name = ETH_MDC +#set_property PACKAGE_PIN C9 [get_ports PhyMdc] + #set_property IOSTANDARD LVCMOS33 [get_ports PhyMdc] +##Bank = 16, Pin name = IO_L14N_T2_SRCC_16, Sch name = ETH_MDIO +#set_property PACKAGE_PIN A9 [get_ports PhyMdio] + #set_property IOSTANDARD LVCMOS33 [get_ports PhyMdio] +##Bank = 35, Pin name = IO_L10P_T1_AD15P_35, Sch name = ETH_RSTN +#set_property PACKAGE_PIN B3 [get_ports PhyRstn] + #set_property IOSTANDARD LVCMOS33 [get_ports PhyRstn] +##Bank = 16, Pin name = IO_L6N_T0_VREF_16, Sch name = ETH_CRSDV +#set_property PACKAGE_PIN D9 [get_ports PhyCrs] + #set_property IOSTANDARD LVCMOS33 [get_ports PhyCrs] +##Bank = 16, Pin name = IO_L13N_T2_MRCC_16, Sch name = ETH_RXERR +#set_property PACKAGE_PIN C10 [get_ports PhyRxErr] + #set_property IOSTANDARD LVCMOS33 [get_ports PhyRxErr] +##Bank = 16, Pin name = IO_L19N_T3_VREF_16, Sch name = ETH_RXD0 +#set_property PACKAGE_PIN D10 [get_ports {PhyRxd[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {PhyRxd[0]}] +##Bank = 16, Pin name = IO_L13P_T2_MRCC_16, Sch name = ETH_RXD1 +#set_property PACKAGE_PIN C11 [get_ports {PhyRxd[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {PhyRxd[1]}] +##Bank = 16, Pin name = IO_L11N_T1_SRCC_16, Sch name = ETH_TXEN +#set_property PACKAGE_PIN B9 [get_ports PhyTxEn] + #set_property IOSTANDARD LVCMOS33 [get_ports PhyTxEn] +##Bank = 16, Pin name = IO_L14P_T2_SRCC_16, Sch name = ETH_TXD0 +#set_property PACKAGE_PIN A10 [get_ports {PhyTxd[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {PhyTxd[0]}] +##Bank = 16, Pin name = IO_L12N_T1_MRCC_16, Sch name = ETH_TXD1 +#set_property PACKAGE_PIN A8 [get_ports {PhyTxd[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {PhyTxd[1]}] +##Bank = 35, Pin name = IO_L11P_T1_SRCC_35, Sch name = ETH_REFCLK +#set_property PACKAGE_PIN D5 [get_ports PhyClk50Mhz] + #set_property IOSTANDARD LVCMOS33 [get_ports PhyClk50Mhz] +##Bank = 16, Pin name = IO_L12P_T1_MRCC_16, Sch name = ETH_INTN +#set_property PACKAGE_PIN B8 [get_ports PhyIntn] + #set_property IOSTANDARD LVCMOS33 [get_ports PhyIntn] + + + +##Quad SPI Flash +##Bank = CONFIG, Pin name = CCLK_0, Sch name = QSPI_SCK +#set_property PACKAGE_PIN E9 [get_ports {QspiSCK}] + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiSCK}] +##Bank = CONFIG, Pin name = IO_L1P_T0_D00_MOSI_14, Sch name = QSPI_DQ0 +#set_property PACKAGE_PIN K17 [get_ports {QspiDB[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}] +##Bank = CONFIG, Pin name = IO_L1N_T0_D01_DIN_14, Sch name = QSPI_DQ1 +#set_property PACKAGE_PIN K18 [get_ports {QspiDB[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}] +##Bank = CONFIG, Pin name = IO_L20_T0_D02_14, Sch name = QSPI_DQ2 +#set_property PACKAGE_PIN L14 [get_ports {QspiDB[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}] +##Bank = CONFIG, Pin name = IO_L2P_T0_D03_14, Sch name = QSPI_DQ3 +#set_property PACKAGE_PIN M14 [get_ports {QspiDB[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}] +##Bank = CONFIG, Pin name = IO_L15N_T2_DQS_DOUT_CSO_B_14, Sch name = QSPI_CSN +#set_property PACKAGE_PIN L13 [get_ports QspiCSn] + #set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn] + + + +##Cellular RAM +##Bank = 14, Pin name = IO_L14N_T2_SRCC_14, Sch name = CRAM_CLK +#set_property PACKAGE_PIN T15 [get_ports RamCLK] + #set_property IOSTANDARD LVCMOS33 [get_ports RamCLK] +##Bank = 14, Pin name = IO_L23P_T3_A03_D19_14, Sch name = CRAM_ADVN +#set_property PACKAGE_PIN T13 [get_ports RamADVn] + #set_property IOSTANDARD LVCMOS33 [get_ports RamADVn] +##Bank = 14, Pin name = IO_L4P_T0_D04_14, Sch name = CRAM_CEN +#set_property PACKAGE_PIN L18 [get_ports RamCEn] + #set_property IOSTANDARD LVCMOS33 [get_ports RamCEn] +##Bank = 15, Pin name = IO_L19P_T3_A22_15, Sch name = CRAM_CRE +#set_property PACKAGE_PIN J14 [get_ports RamCRE] + #set_property IOSTANDARD LVCMOS33 [get_ports RamCRE] +##Bank = 15, Pin name = IO_L15P_T2_DQS_15, Sch name = CRAM_OEN +#set_property PACKAGE_PIN H14 [get_ports RamOEn] + #set_property IOSTANDARD LVCMOS33 [get_ports RamOEn] +##Bank = 14, Pin name = IO_0_14, Sch name = CRAM_WEN +#set_property PACKAGE_PIN R11 [get_ports RamWEn] + #set_property IOSTANDARD LVCMOS33 [get_ports RamWEn] +##Bank = 15, Pin name = IO_L24N_T3_RS0_15, Sch name = CRAM_LBN +#set_property PACKAGE_PIN J15 [get_ports RamLBn] + #set_property IOSTANDARD LVCMOS33 [get_ports RamLBn] +##Bank = 15, Pin name = IO_L17N_T2_A25_15, Sch name = CRAM_UBN +#set_property PACKAGE_PIN J13 [get_ports RamUBn] + #set_property IOSTANDARD LVCMOS33 [get_ports RamUBn] +##Bank = 14, Pin name = IO_L14P_T2_SRCC_14, Sch name = CRAM_WAIT +#set_property PACKAGE_PIN T14 [get_ports RamWait] + #set_property IOSTANDARD LVCMOS33 [get_ports RamWait] + +##Bank = 14, Pin name = IO_L5P_T0_DQ06_14, Sch name = CRAM_DQ0 +#set_property PACKAGE_PIN R12 [get_ports {MemDB[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[0]}] +##Bank = 14, Pin name = IO_L19P_T3_A10_D26_14, Sch name = CRAM_DQ1 +#set_property PACKAGE_PIN T11 [get_ports {MemDB[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[1]}] +##Bank = 14, Pin name = IO_L20P_T3_A08)D24_14, Sch name = CRAM_DQ2 +#set_property PACKAGE_PIN U12 [get_ports {MemDB[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[2]}] +##Bank = 14, Pin name = IO_L5N_T0_D07_14, Sch name = CRAM_DQ3 +#set_property PACKAGE_PIN R13 [get_ports {MemDB[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[3]}] +##Bank = 14, Pin name = IO_L17N_T2_A13_D29_14, Sch name = CRAM_DQ4 +#set_property PACKAGE_PIN U18 [get_ports {MemDB[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[4]}] +##Bank = 14, Pin name = IO_L12N_T1_MRCC_14, Sch name = CRAM_DQ5 +#set_property PACKAGE_PIN R17 [get_ports {MemDB[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[5]}] +##Bank = 14, Pin name = IO_L7N_T1_D10_14, Sch name = CRAM_DQ6 +#set_property PACKAGE_PIN T18 [get_ports {MemDB[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[6]}] +##Bank = 14, Pin name = IO_L7P_T1_D09_14, Sch name = CRAM_DQ7 +#set_property PACKAGE_PIN R18 [get_ports {MemDB[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[7]}] +##Bank = 15, Pin name = IO_L22N_T3_A16_15, Sch name = CRAM_DQ8 +#set_property PACKAGE_PIN F18 [get_ports {MemDB[8]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[8]}] +##Bank = 15, Pin name = IO_L22P_T3_A17_15, Sch name = CRAM_DQ9 +#set_property PACKAGE_PIN G18 [get_ports {MemDB[9]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[9]}] +##Bank = 15, Pin name = IO_IO_L18N_T2_A23_15, Sch name = CRAM_DQ10 +#set_property PACKAGE_PIN G17 [get_ports {MemDB[10]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[10]}] +##Bank = 14, Pin name = IO_L4N_T0_D05_14, Sch name = CRAM_DQ11 +#set_property PACKAGE_PIN M18 [get_ports {MemDB[11]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[11]}] +##Bank = 14, Pin name = IO_L10N_T1_D15_14, Sch name = CRAM_DQ12 +#set_property PACKAGE_PIN M17 [get_ports {MemDB[12]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[12]}] +##Bank = 14, Pin name = IO_L9N_T1_DQS_D13_14, Sch name = CRAM_DQ13 +#set_property PACKAGE_PIN P18 [get_ports {MemDB[13]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[13]}] +##Bank = 14, Pin name = IO_L9P_T1_DQS_14, Sch name = CRAM_DQ14 +#set_property PACKAGE_PIN N17 [get_ports {MemDB[14]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[14]}] +##Bank = 14, Pin name = IO_L12P_T1_MRCC_14, Sch name = CRAM_DQ15 +#set_property PACKAGE_PIN P17 [get_ports {MemDB[15]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[15]}] + +##Bank = 15, Pin name = IO_L23N_T3_FWE_B_15, Sch name = CRAM_A0 +#set_property PACKAGE_PIN J18 [get_ports {MemAdr[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[0]}] +##Bank = 15, Pin name = IO_L18P_T2_A24_15, Sch name = CRAM_A1 +#set_property PACKAGE_PIN H17 [get_ports {MemAdr[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[1]}] +##Bank = 15, Pin name = IO_L19N_T3_A21_VREF_15, Sch name = CRAM_A2 +#set_property PACKAGE_PIN H15 [get_ports {MemAdr[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[2]}] +##Bank = 15, Pin name = IO_L23P_T3_FOE_B_15, Sch name = CRAM_A3 +#set_property PACKAGE_PIN J17 [get_ports {MemAdr[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[3]}] +##Bank = 15, Pin name = IO_L13P_T2_MRCC_15, Sch name = CRAM_A4 +#set_property PACKAGE_PIN H16 [get_ports {MemAdr[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[4]}] +##Bank = 15, Pin name = IO_L24P_T3_RS1_15, Sch name = CRAM_A5 +#set_property PACKAGE_PIN K15 [get_ports {MemAdr[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[5]}] +##Bank = 15, Pin name = IO_L17P_T2_A26_15, Sch name = CRAM_A6 +#set_property PACKAGE_PIN K13 [get_ports {MemAdr[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[6]}] +##Bank = 14, Pin name = IO_L11P_T1_SRCC_14, Sch name = CRAM_A7 +#set_property PACKAGE_PIN N15 [get_ports {MemAdr[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[7]}] +##Bank = 14, Pin name = IO_L16N_T2_SRCC-14, Sch name = CRAM_A8 +#set_property PACKAGE_PIN V16 [get_ports {MemAdr[8]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[8]}] +##Bank = 14, Pin name = IO_L22P_T3_A05_D21_14, Sch name = CRAM_A9 +#set_property PACKAGE_PIN U14 [get_ports {MemAdr[9]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[9]}] +##Bank = 14, Pin name = IO_L22N_T3_A04_D20_14, Sch name = CRAM_A10 +#set_property PACKAGE_PIN V14 [get_ports {MemAdr[10]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[10]}] +##Bank = 14, Pin name = IO_L20N_T3_A07_D23_14, Sch name = CRAM_A11 +#set_property PACKAGE_PIN V12 [get_ports {MemAdr[11]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[11]}] +##Bank = 14, Pin name = IO_L8N_T1_D12_14, Sch name = CRAM_A12 +#set_property PACKAGE_PIN P14 [get_ports {MemAdr[12]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[12]}] +##Bank = 14, Pin name = IO_L18P_T2_A12_D28_14, Sch name = CRAM_A13 +#set_property PACKAGE_PIN U16 [get_ports {MemAdr[13]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[13]}] +##Bank = 14, Pin name = IO_L13N_T2_MRCC_14, Sch name = CRAM_A14 +#set_property PACKAGE_PIN R15 [get_ports {MemAdr[14]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[14]}] +##Bank = 14, Pin name = IO_L8P_T1_D11_14, Sch name = CRAM_A15 +#set_property PACKAGE_PIN N14 [get_ports {MemAdr[15]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[15]}] +##Bank = 14, Pin name = IO_L11N_T1_SRCC_14, Sch name = CRAM_A16 +#set_property PACKAGE_PIN N16 [get_ports {MemAdr[16]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[16]}] +##Bank = 14, Pin name = IO_L6N_T0_D08_VREF_14, Sch name = CRAM_A17 +#set_property PACKAGE_PIN M13 [get_ports {MemAdr[17]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[17]}] +##Bank = 14, Pin name = IO_L18N_T2_A11_D27_14, Sch name = CRAM_A18 +#set_property PACKAGE_PIN V17 [get_ports {MemAdr[18]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[18]}] +##Bank = 14, Pin name = IO_L17P_T2_A14_D30_14, Sch name = CRAM_A19 +#set_property PACKAGE_PIN U17 [get_ports {MemAdr[19]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[19]}] +##Bank = 14, Pin name = IO_L24N_T3_A00_D16_14, Sch name = CRAM_A20 +#set_property PACKAGE_PIN T10 [get_ports {MemAdr[20]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[20]}] +##Bank = 14, Pin name = IO_L10P_T1_D14_14, Sch name = CRAM_A21 +#set_property PACKAGE_PIN M16 [get_ports {MemAdr[21]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[21]}] +##Bank = 14, Pin name = IO_L23N_T3_A02_D18_14, Sch name = CRAM_A22 +#set_property PACKAGE_PIN U13 [get_ports {MemAdr[22]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[22]}] \ No newline at end of file diff --git a/ripestohex.py b/ripestohex.py new file mode 100644 index 0000000..173e293 --- /dev/null +++ b/ripestohex.py @@ -0,0 +1,30 @@ + +if __name__ == "__main__": + ripes: str = """ + +00000000 : + 0: 00100093 00000000000100000000000010010011 + 4: 00000133 00000000000000000000000100110011 + 8: 000001b3 00000000000000000000000110110011 + c: 7ff00213 01111111111100000000001000010011 + 10: 00521213 00000000010100100001001000010011 + +00000014 : + 14: 00110133 00000000000100010000000100110011 + 18: 000001b3 00000000000000000000000110110011 + +0000001c : + 1c: 001181b3 00000000000100011000000110110011 + 20: fe41fae3 11111110010000011111101011100011 + 24: ff9ff0ef 11111111100111111111000011101111 +""" + raw = ripes.split(" ") + cmd: list = [] + for i in raw: + if len(i) == 8: + cmd.append(i) + final: str = "" + for i in cmd: + final += f"x\"{i}\", " + final += "others => (others => '0')" + print(final) diff --git a/src/alu.vhd b/src/alu.vhd new file mode 100644 index 0000000..972b6a7 --- /dev/null +++ b/src/alu.vhd @@ -0,0 +1,53 @@ +-- alu.vhd +-- Created on: Mo 21. Nov 11:23:36 CET 2022 +-- Author(s): Carl Ries, Yannick Reiß, Alexander Graf +-- Content: ALU +library IEEE; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.riscv_types.all; + +entity alu is + port ( + alu_opc : in aluOP; -- alu opcode. + input1 : in word; -- input1 of alu (reg1 / pc address) rs1 + input2 : in word; -- input2 of alu (reg2 / immediate) rs2 + result : out word -- alu output. + ); +end alu; + +-- Architecture implementation of alu: implements operatings mode +architecture implementation of alu is + +begin + -- Process log that fetches the opcode and executes it + log : process (alu_opc, input1, input2) -- runs only, when all changed + begin + case alu_opc is + when uNOP => result <= std_logic_vector(to_unsigned(0, wordWidth)); -- no operations + when uADD => result <= std_logic_vector(unsigned(input1) + unsigned( input2 )); -- addition + when uSUB => result <= std_logic_vector(signed(input1) - signed( input2 )); -- subtraction + when uSLL => result <= std_logic_vector(unsigned(input1) sll 1); -- shift left logical + when uSLT => + if(signed( input1 ) < signed( input2 )) then + result <= std_logic_vector(to_unsigned(1, wordWidth)); + else + result <= std_logic_vector(to_unsigned(0, wordWidth)); + end if; -- Set lower than + when uSLTU => + if(unsigned( input1 ) < unsigned( input2 )) then + result <= std_logic_vector(to_unsigned(1, wordWidth)); + else + result <= std_logic_vector(to_unsigned(0, wordWidth)); + end if; -- Set lower than unsigned + when uXOR => result <= input1 xor input2; -- exclusive or + when uSRL => result <= std_logic_vector(unsigned(input1) srl 1); -- shift right logical + when uSRA => result <= std_logic_vector(to_stdlogicvector(to_bitvector(input1) sra 1)); -- shift right arithmetic + when uOR => result <= input1 or input2; -- or + when uAND => result <= input1 and input2; -- and + when others => result <= std_logic_vector(to_unsigned(0, wordWidth)); -- other operations return zero + end case; + end process; +end implementation; diff --git a/src/branch.vhd b/src/branch.vhd new file mode 100644 index 0000000..4b06619 --- /dev/null +++ b/src/branch.vhd @@ -0,0 +1,69 @@ +-- branch.vhd +-- Created on: 19:01:2023 +-- Author(s): Yannick Reiß +-- Copyright: WTFPL +-- Content: Entity branch - enable B-types in CPU +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library work; +use work.riscv_types.all; + +entity Branch is + port ( + op_code : in uOP; + reg1 : in word; + reg2 : in word; + jmp_enable : out one_bit + ); +end Branch; + +architecture arch of Branch is + +begin + + branch_process : process(op_code) + begin + case op_code is + when uBEQ => + if reg1 = reg2 then + jmp_enable <= "1"; + else + jmp_enable <= "0"; + end if; + when uBNE => + if not (reg1 = reg2) then + jmp_enable <= "1"; + else + jmp_enable <= "0"; + end if; + when uBLT => + if signed(reg1) < signed(reg2) then + jmp_enable <= "1"; + else + jmp_enable <= "0"; + end if; + when uBGE => + if signed(reg1) >= signed(reg2) then + jmp_enable <= "1"; + else + jmp_enable <= "0"; + end if; + when uBLTU => + if unsigned(reg1) < unsigned(reg2) then + jmp_enable <= "1"; + else + jmp_enable <= "0"; + end if; + when uBGEU => + if unsigned(reg1) >= unsigned(reg2) then + jmp_enable <= "1"; + else + jmp_enable <= "0"; + end if; + when others => + jmp_enable <= "0"; + end case; + end process; -- branch +end architecture; -- arch diff --git a/src/cpu.vhd b/src/cpu.vhd new file mode 100644 index 0000000..db64967 --- /dev/null +++ b/src/cpu.vhd @@ -0,0 +1,359 @@ +-- cpu.vhd +-- Created on: Mo 19. Dez 11:07:17 CET 2022 +-- Author(s): Yannick Reiß, Carl Ries, Alexander Graf +-- Content: Entity cpu +library IEEE; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.riscv_types.all; + +-- Entity cpu: path implementation of RISC-V cpu +entity cpu is + port( + clk : in std_logic; -- clk to control the unit + + -- Led Output + led : out std_logic_vector(15 downto 0); -- output to 16 LEDS + + -- RGB Output + RGB1 : out std_logic_vector(2 downto 0); -- output to RGB 1 + RGB2 : out std_logic_vector(2 downto 0) -- output to RGB 2 + ); +end cpu; + +-- Architecture implementation of c: control and connect different parts of cpu +architecture implementation of cpu is + + component pc + port( + clk : in std_logic; -- Clock input for timing + en_pc : in one_bit; -- activates PC + addr_calc : in ram_addr_t; -- Address from ALU + doJump : in one_bit; -- Jump to Address + addr : out ram_addr_t -- Address to Decoder + ); + end component; + + component ram + port( + clk : in std_logic; -- Clock input for timing + instructionAdr : in ram_addr_t; -- Address instruction + dataAdr : in ram_addr_t; -- Address data + writeEnable : in one_bit; -- Read or write mode + dataIn : in word; -- Write data + instruction : out word; -- Get instruction + dataOut : out word -- Read data + ); + end component; + + component alu + port ( + alu_opc : in aluOP; -- alu opcode. + input1 : in word; -- input1 of alu (reg1 / pc address) rs1 + input2 : in word; -- input2 of alu (reg2 / immediate) rs2 + result : out word -- alu output. + ); + end component; + + component decoder + port( + instrDecode : in instruction; -- Instruction from instruction memory + op_code : out uOP; -- alu opcode + regOp1 : out reg_idx; -- Rj: first register to read + regOp2 : out reg_idx; -- Rk: second register to read + regWrite : out reg_idx -- Ri: the register to write to + ); + end component; + + component imm + port ( + instruction : in instruction; + opcode : in uOP; + immediate : out word + ); + end component; + + component registers + port( + clk : in std_logic; -- input for clock (control device) + en_reg_wb : in one_bit; -- enable register write back (?) + data_in : in word; -- Data to be written into the register + wr_idx : in reg_idx; -- register to write to + r1_idx : in reg_idx; -- first register to read from + r2_idx : in reg_idx; -- second register to read from + write_enable : in one_bit; -- enable writing to wr_idx + r1_out : out word; -- data from first register + r2_out : out word; -- data from second register + led_out : out word -- output led + ); + end component; + + component Branch + port( + op_code : in uOP; + reg1 : in word; + reg2 : in word; + jmp_enable : out one_bit + ); + end component; + + -- SIGNALS GLOBAL + signal s_clock : std_logic; + signal s_reg_wb_enable : one_bit; --enables: register writeback + signal s_reg_wr_enable : one_bit; --enables: register write to index + signal s_pc_enable : one_bit; --enables: pc + signal s_pc_jump_enable : one_bit; --enables: pc jump to address + signal s_ram_enable : one_bit; --enables: ram write enalbe + signal s_led_out : word := "10110011100001110111010110101110"; -- stores the exact output + + + + -- decoder -> registers + signal s_idx_1 : reg_idx; + signal s_idx_2 : reg_idx; + signal s_idx_wr : reg_idx; + + -- decoder -> imm ( + decoder) + signal s_opcode : uOP; + + -- register -> alu + signal s_reg_data1 : word; + signal s_reg_data2 : word; + + -- pc -> ram + signal s_instAdr : ram_addr_t; + signal s_cycle_cnt : cpuStates := stIF; + signal s_branch_jump_enable : one_bit; + + -- alu -> ram + register + signal s_alu_data : word; + + -- ram -> register + signal s_ram_data : word; + + --ram -> decoder + imm + signal s_inst : instruction; + signal s_data_in_addr : ram_addr_t; + + + + -- v dummy signals below v + + --imm -> ??? + signal s_immediate : word; + + -- ??? -> alu + signal X_aluOP : aluOP; + + -- ??? -> alu + signal X_addr_calc : ram_addr_t; + + -- Clock signals + signal reset : std_logic; + signal locked : std_logic; + +------------------------- +-- additional ALU signals +------------------------- + signal aluIn1 : word; + signal aluIn2 : word; + +------------------------- +-- additional REG signals +------------------------- + signal reg_data_in : word; + +begin + + s_clock <= clk; + + decoder_RISCV : decoder + port map( + instrDecode => s_inst, + op_code => s_opcode, + regOp1 => s_idx_1, + regOp2 => s_idx_2, + regWrite => s_idx_wr + ); + + registers_RISCV : registers + port map( + clk => s_clock, + en_reg_wb => s_reg_wb_enable, + data_in => reg_data_in, + wr_idx => s_idx_wr, + r1_idx => s_idx_1, + r2_idx => s_idx_2, + write_enable => s_reg_wr_enable, + r1_out => s_reg_data1, + r2_out => s_reg_data2, + led_out => s_led_out + ); + + imm_RISCV : imm + port map( + instruction => s_inst, + opcode => s_opcode, + immediate => s_immediate + ); + + pc_RISCV : pc + port map( + clk => s_clock, + en_pc => s_pc_enable, + addr_calc => X_addr_calc, + doJump => s_pc_jump_enable, + addr => s_instAdr + ); + + alu_RISCV : alu + port map( + alu_opc => X_aluOP, -- switch case from s_opcode + input1 => aluIn1, + input2 => aluIn2, + result => s_alu_data + ); + + ram_RISCV : ram + port map( + clk => s_clock, -- + instructionAdr => s_instAdr, -- instruction from pc + dataAdr => s_data_in_addr, -- data address from alu + writeEnable => s_ram_enable, -- + dataIn => s_reg_data2, -- data from register + instruction => s_inst, -- + dataOut => s_ram_data + ); + + branch_RISCV : Branch + port map( + op_code => s_opcode, + reg1 => aluIn1, + reg2 => aluIn2, + jmp_enable => s_branch_jump_enable + ); + +------------------------ +-- ALU opcode and input connection +------------------------ + -- Process alu_control set alu opcode + + ----------------------------------------- + -- Output + ----------------------------------------- + led <= s_led_out(15 downto 0); + RGB1 <= s_clock & s_clock & s_clock; + + alu_control : process (s_immediate, s_opcode, s_reg_data1, s_reg_data2) -- runs only, when item in list changed + begin + -- Connect opcode + case s_opcode is + when uADD | uADDI => X_aluOP <= uADD; + when uSUB => X_aluOP <= uSUB; + when uSLL | uSLLI => X_aluOP <= uSLL; + when uSLT | uSLTI => X_aluOP <= uSLT; + when uSLTU | uSLTIU => X_aluOP <= uSLTU; + when uXOR | uXORI => X_aluOP <= uXOR; + when uSRL | uSRLI => X_aluOP <= uSRL; + when uSRA | uSRAI => X_aluOP <= uSRA; + when uOR | uORI => X_aluOP <= uOR; + when uAND | uANDI => X_aluOP <= uAND; + when others => X_aluOP <= uNOP; + end case; + -- connect input1 + case s_opcode is + -- add nonstandard inputs for aluIn1 here + when others => aluIn1 <= s_reg_data1; + end case; + + -- TODO: why line from pc to alu inp1? + -- connect input 2 + case s_opcode is + when uADDI | uSLTI | uSLTIU | uXORI | uORI | uANDI => aluIn2 <= s_immediate; + when others => aluIn2 <= s_reg_data2; -- use rs2 as default + end case; + end process; + + -- Process register_data_input select which input is needed for register + register_data_input : process (s_cycle_cnt, s_opcode, s_ram_data, s_alu_data) -- runs only, when item in list changed + begin + s_reg_wb_enable <= "0"; + case s_opcode is + when uBEQ | uBNE | uBLT | uBGE | uBLTU | uBGEU | uSB | uSH | uSW | uECALL | uNOP => s_reg_wr_enable <= "0"; + when others => + if s_cycle_cnt = stEXEC then + s_reg_wr_enable <= "1"; + else + s_reg_wr_enable <= "0"; + end if; + end case; + + case s_opcode is + when uLB | uLH | uLW | uLBU | uLHU => reg_data_in <= s_ram_data; -- use value from + -- RAM (Load instructions) + when others => reg_data_in <= s_alu_data; -- alu operations as default + end case; + end process; + + -- Process pc input + pc_addr_input : process(s_opcode, s_cycle_cnt, s_instAdr, s_immediate) + begin + if s_cycle_cnt = stWB then + s_pc_enable <= "1"; + else + s_pc_enable <= "0"; + -- X_addr_calc <= s_instAdr; -- should not be necessary, every case option sets X_addr_calc + end if; + case s_opcode is + when uJALR | uJAL => + s_pc_jump_enable <= "1"; + X_addr_calc <= std_logic_vector(signed(s_immediate(11 downto 0)) + signed(s_instAdr)); + + -- Branch op_codes + when uBEQ | uBNE | uBLT | uBGE | uBLTU | uBGEU => + -- always load address from immediate on B-Type + X_addr_calc <= std_logic_vector(signed(s_immediate(11 downto 0)) + signed(s_instAdr)); + -- check for opcodes and evaluate condition + s_pc_jump_enable <= s_branch_jump_enable; + when others => + s_pc_jump_enable <= "0"; + X_addr_calc <= s_instAdr; + end case; + end process; + + -- process ram + ram_input : process(s_opcode, s_cycle_cnt) + begin + s_data_in_addr <= std_logic_vector(signed(s_immediate(11 downto 0)) + signed(s_reg_data1(11 downto 0))); + if s_cycle_cnt = stWB then + case s_opcode is + when uSB | uSH | uSW => s_ram_enable <= "1"; + when others => s_ram_enable <= "0"; + end case; + else + s_ram_enable <= "0"; + end if; + end process; + + -- pc cycle control + pc_cycle_control : process(s_clock) + begin + if rising_edge(s_clock) then + case s_cycle_cnt is + when stIF => s_cycle_cnt <= stDEC; + RGB2 <= "001"; + when stDEC => s_cycle_cnt <= stOF; + RGB2 <= "010"; + when stOF => s_cycle_cnt <= stEXEC; + RGB2 <= "011"; + when stEXEC => s_cycle_cnt <= stWB; + RGB2 <= "100"; + when others => s_cycle_cnt <= stIF; + RGB2 <= "101"; + end case; + end if; + end process pc_cycle_control; + +end implementation; diff --git a/src/decoder.vhd b/src/decoder.vhd new file mode 100644 index 0000000..ac5ad8e --- /dev/null +++ b/src/decoder.vhd @@ -0,0 +1,125 @@ +-- vsg_off +-- decoder_reloaded.vhd +-- Created on: Do 8. Dez 18:45:24 CET 2022 +-- Author(s): Axel, Carsten und Jannis +-- Content: Decoder Version 2 (ständige vollbelegung) + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.riscv_types.all; + +-- Entity decode: Decoder currently supporting read operations +entity decoder is + port( + instrDecode : in instruction; -- Instruction from instruction memory + op_code : out uOP; -- alu opcode + regOp1 : out reg_idx; -- Rj: first register to read + regOp2 : out reg_idx; -- Rk: second register to read + regWrite : out reg_idx -- Ri: the register to write to + ); +end decoder; + +-- Architecture schematic of decode: Split up instruction into registers +architecture decode of decoder is + +begin + + -- Process decode splits up instruction for alu + process (instrDecode(11 downto 7), instrDecode(14 downto 12), + instrDecode(19 downto 15), instrDecode(24 downto 20), + instrDecode(31 downto 25), instrDecode(6 downto 0)) -- runs only, when instrDecode changed + begin + -- ONLY DECODES RV32I Base Instruction Set + -- op_code (funct7 + funct3 + operand) + case instrDecode(6 downto 0) is + -- R-Type + when "0110011" => + case instrDecode(14 downto 12) is + when "000" => + if instrDecode(31 downto 25) = "0000000" then + op_code <= uADD; + else + op_code <= uSUB; + end if; -- ADD / SUB + when "001" => op_code <= uSLL; + when "010" => op_code <= uSLT; + when "011" => op_code <= uSLTU; + when "100" => op_code <= uXOR; + when "101" => + if instrDecode(31 downto 25) = "0000000" then + op_code <= uSRL; + else + op_code <= uSRA; + end if; + when "110" => op_code <= uOR; + when "111" => op_code <= uAND; + when others => op_code <= uNOP; + end case; + + -- I-Type + when "1100111" => op_code <= uJALR; + when "0000011" => + case instrDecode(14 downto 12) is + when "000" => op_code <= uLB; + when "001" => op_code <= uLH; + when "010" => op_code <= uLW; + when "100" => op_code <= uLBU; + when "101" => op_code <= uLHU; + when others => op_code <= uNOP; + end case; + when "0010011" => + case instrDecode(14 downto 12) is + when "000" => op_code <= uADDI; + when "001" => op_code <= uSLTI; + when "010" => op_code <= uSLTIU; + when "011" => op_code <= uXORI; + when "100" => op_code <= uORI; + when "101" => op_code <= uANDI; + when others => op_code <= uNOP; + end case; + + -- S-Type + when "0100011" => + case instrDecode(14 downto 12) is + when "000" => op_code <= uSB; + when "001" => op_code <= uSH; + when "010" => op_code <= uSW; + when others => op_code <= uNOP; + end case; + + -- B-Type + when "1100011" => + case instrDecode(14 downto 12) is + when "000" => op_code <= uBEQ; + when "001" => op_code <= uBNE; + when "100" => op_code <= uBLT; + when "101" => op_code <= uBGE; + when "110" => op_code <= uBLTU; + when "111" => op_code <= uBGEU; + when others => op_code <= uNOP; + end case; + + -- U-Type + when "0110111" => op_code <= uLUI; + when "0010111" => op_code <= uAUIPC; + + -- J-Type + when "1101111" => op_code <= uJAL; + + -- Add more Operandtypes here + when others => op_code <= uNOP; + end case; + + -- regOp1 (19-15) + regOp1 <= instrDecode(19 downto 15); + + -- regOp2 (24-20) + regOp2 <= instrDecode(24 downto 20); + + -- regWrite (11-7) + regWrite <= instrDecode(11 downto 7); + end process; +end decode; diff --git a/src/imem.vhd b/src/imem.vhd new file mode 100644 index 0000000..f1fb5b6 --- /dev/null +++ b/src/imem.vhd @@ -0,0 +1,54 @@ +-- imem.vhd +-- Created on: Do 29. Dez 20:44:53 CET 2022 +-- Author(s): Yannick Reiß, Alexander Graf, Carl Ries +-- Content: Entity instruction memory as part of ram +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.riscv_types.all; + +entity instr_memory is + + generic (initMem : ram_t := (others => (others => '0'))); + + port (clk : in std_logic; + + addr_a : in std_logic_vector(ram_addr_size - 3 downto 0); + data_read_a : out std_logic_vector(wordWidth - 1 downto 0); + + write_b : in one_bit; + addr_b : in std_logic_vector(ram_addr_size - 3 downto 0); + data_read_b : out std_logic_vector(wordWidth - 1 downto 0); + data_write_b : in std_logic_vector(wordWidth - 1 downto 0) + + ); + +end instr_memory; + +-- START: +-- addi x1 x0 1 +-- add x2 x0 x0 +-- add x3 x0 x0 +-- addi x4 x0 2047 +-- slli x4 x4 5 +-- REG2UP: +-- add x2 x2 x1 +-- add x3 x0 x0 +-- REG3UP: +-- add x3 x3 x1 +-- bgeu x3 x4 REG2UP +-- jal REG3UP +architecture behavioral of instr_memory is + signal store : ram_t := + ( + x"00100093", x"00000133", x"000001b3", x"7ff00213", x"00521213", x"00110133", x"000001b3", x"001181b3", x"fe41fae3", x"ff9ff0ef", others => (others => '0') + ); +begin + + -- Two synchron read ports + data_read_a <= store(to_integer(unsigned(addr_a(9 downto 2)))); + data_read_b <= store(to_integer(unsigned(addr_b(9 downto 2)))); + +end behavioral; diff --git a/src/imm.vhd b/src/imm.vhd new file mode 100644 index 0000000..f690364 --- /dev/null +++ b/src/imm.vhd @@ -0,0 +1,44 @@ +library IEEE; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.riscv_types.all; + +entity imm is + port ( + instruction : in instruction; + opcode : in uOP; + immediate : out word + ); +end imm; + +-- Architecture slicing of imm: slices immediate out of instruction +architecture slicing of imm is + +begin + -- Process immediate slice + process (opcode, instruction) + begin + case opcode is + -- I-Type + when uLB | uLH | uLW | uLBU | uLHU | uADDI | uSLTI | uSLTIU | uXORI | uORI | uANDI => immediate <= std_logic_vector(to_unsigned(0, wordWidth - 12)) & instruction(31 downto 20); + + -- S-Type + when uSB | uSH | uSW => immediate <= std_logic_vector(to_unsigned(0, wordWidth-12)) & instruction(31 downto 25) & instruction(11 downto 7); + + -- B-Type + when uBEQ | uBNE | uBLT | uBGE | uBLTU | uBGEU => immediate <= std_logic_vector(to_unsigned(0, 19)) & instruction(31) & instruction(7) & instruction(30 downto 25) & instruction(11 downto 8) & "0"; + + -- U-Type + when uLUI | uAUIPC => immediate <= instruction(31 downto 12) & std_logic_vector(to_unsigned(0, 12)); + + -- J-Type + when uJAL => immediate <= std_logic_vector(to_unsigned(0, wordWidth - 21)) & instruction(31) & instruction(19 downto 12) & instruction(20) & instruction(30 downto 21) & "0"; + + when others => immediate <= x"C000FFEE"; + end case; + end process; + +end slicing; + diff --git a/src/pc.vhd b/src/pc.vhd new file mode 100644 index 0000000..4b595d0 --- /dev/null +++ b/src/pc.vhd @@ -0,0 +1,46 @@ +-- pc.vhd +-- Created on: Mo 05. Dec 14:21:39 CET 2022 +-- Author(s): Carl Ries, Yannick Reiß, Alexander Graf +-- Content: program counter +library IEEE; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.riscv_types.all; + +-- Entity PC: entity defining the pins and ports of the programmcounter +entity pc is + port (clk : in std_logic; -- Clock input for timing + en_pc : in one_bit; -- activates PC + addr_calc : in ram_addr_t; -- Address from ALU + doJump : in one_bit; -- Jump to Address + addr : out ram_addr_t -- Address to Decoder + ); + +end PC; + + +architecture pro_count of pc is + signal addr_out : ram_addr_t := (others => '0'); + signal addr_out_plus : ram_addr_t := (others => '0'); +begin + process (clk) + begin + if rising_edge(clk) then + if en_pc = "1" then + -- count + if doJump = "1" then + addr_out <= addr_calc; + -- jump + else + addr_out <= addr_out_plus; + end if; + end if; + end if; + end process; + + addr_out_plus <= (std_logic_vector(to_unsigned(to_integer(unsigned(addr_out)) + 4, ram_addr_size))); + addr <= addr_out; + +end pro_count; diff --git a/src/ram_block.vhd b/src/ram_block.vhd new file mode 100755 index 0000000..91e413d --- /dev/null +++ b/src/ram_block.vhd @@ -0,0 +1,54 @@ +-- ram_block.vhd +-- Created on: Do 3. Nov 20:06:13 CET 2022 +-- Author(s): Alexander Graf, Carl Ries, Yannick Reiß +-- Content: Entity ram_block +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.riscv_types.all; + +entity ram_block is + + generic (initMem : ram_t := (others => (others => '0'))); + + port (clk : in std_logic; + + addr_a : in std_logic_vector(ram_addr_size - 3 downto 0); + data_read_a : out std_logic_vector(wordWidth - 1 downto 0); + + write_b : in one_bit; + addr_b : in std_logic_vector(ram_addr_size - 3 downto 0); + data_read_b : out std_logic_vector(wordWidth - 1 downto 0); + data_write_b : in std_logic_vector(wordWidth - 1 downto 0) + + ); + +end ram_block; + +-- +architecture behavioral of ram_block is + + signal store : ram_t := initMem; + +begin + + process(clk) + begin + if rising_edge(clk) then + + -- One synchron write port + if write_b = "1" then + store(to_integer(unsigned(addr_b(9 downto 2)))) <= data_write_b; + end if; + + end if; + end process; + + -- Two synchron read ports + data_read_a <= store(to_integer(unsigned(addr_a(9 downto 2)))); + data_read_b <= store(to_integer(unsigned(addr_b(9 downto 2)))); + +end behavioral; + diff --git a/src/ram_entity_only.vhd b/src/ram_entity_only.vhd new file mode 100755 index 0000000..9963809 --- /dev/null +++ b/src/ram_entity_only.vhd @@ -0,0 +1,147 @@ +-- Created on: Do 3. Nov 20:11:50 CET 2022 +-- Author(s): Alexander Graf, Carl Ries, Yannick Reiß +-- Content: Entity ram and architecture of ram +library work; +use work.riscv_types.all; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- Entity ram: Ram storage +entity ram is + + generic (zeros : ram_t := (others => (others => '0'))); + port( + clk : in std_logic; -- Clock input for timing + instructionAdr : in ram_addr_t; -- Address instruction + dataAdr : in ram_addr_t; -- Address data + + writeEnable : in one_bit; -- Read or write mode + + dataIn : in word; -- Write data + instruction : out word; -- Get instruction + dataOut : out word -- Read data + ); +end ram; + +-- Architecture behavioral of ram: control different ram blocks +architecture behavioral of ram is + -- write signals + signal wr1 : one_bit := "0"; + signal wr2 : one_bit := "0"; + signal wr3 : one_bit := "0"; + signal wr4 : one_bit := "0"; + + -- instruction signals + signal inst1 : std_logic_vector(wordWidth - 1 downto 0); + signal inst2 : std_logic_vector(wordWidth - 1 downto 0); + signal inst3 : std_logic_vector(wordWidth - 1 downto 0); + signal inst4 : std_logic_vector(wordWidth - 1 downto 0); + + -- data signals + signal data1 : std_logic_vector(wordWidth - 1 downto 0); + signal data2 : std_logic_vector(wordWidth - 1 downto 0); + signal data3 : std_logic_vector(wordWidth - 1 downto 0); + signal data4 : std_logic_vector(wordWidth - 1 downto 0); + +begin + + block1 : entity work.instr_memory(behavioral) + port map ( + clk => clk, + addr_a => instructionAdr(ram_addr_size - 3 downto 0), + write_b => wr1, + addr_b => dataAdr(ram_addr_size - 3 downto 0), + data_write_b => dataIn, + + data_read_a => inst1, + data_read_b => data1 + ); + + block2 : entity work.ram_block(behavioral) + port map ( + clk => clk, + addr_a => instructionAdr(9 downto 0), + write_b => wr2, + addr_b => dataAdr(9 downto 0), + data_write_b => dataIn, + + data_read_a => inst2, + data_read_b => data2 + ); + + block3 : entity work.ram_block(behavioral) + port map ( + clk => clk, + addr_a => instructionAdr(9 downto 0), + write_b => wr3, + addr_b => dataAdr(9 downto 0), + data_write_b => dataIn, + + data_read_a => inst3, + data_read_b => data3 + ); + + block4 : entity work.ram_block(behavioral) + port map ( + clk => clk, + addr_a => instructionAdr(9 downto 0), + write_b => wr4, + addr_b => dataAdr(9 downto 0), + data_write_b => dataIn, + + data_read_a => inst4, + data_read_b => data4 + ); + + addr_block : process (data1, data2, data3, data4, dataAdr(11 downto 10), + inst1, inst2, inst3, inst4, + instructionAdr(11 downto 10), writeEnable) -- run process addr_block when list changes + begin + -- enable write + case dataAdr(11 downto 10) is + when "00" => + wr1 <= writeEnable; + wr2 <= "0"; + wr3 <= "0"; + wr4 <= "0"; + when "01" => + wr1 <= "0"; + wr2 <= writeEnable; + wr3 <= "0"; + wr4 <= "0"; + when "10" => + wr1 <= "0"; + wr2 <= "0"; + wr3 <= writeEnable; + wr4 <= "0"; + when "11" => + wr1 <= "0"; + wr2 <= "0"; + wr3 <= "0"; + wr4 <= writeEnable; + when others => + wr1 <= "0"; + wr2 <= "0"; + wr3 <= "0"; + wr4 <= "0"; + end case; + + -- instruction data + case instructionAdr(11 downto 10) is + when "00" => instruction <= inst1; + when "01" => instruction <= inst2; + when "10" => instruction <= inst3; + when others => instruction <= inst4; + end case; + + -- data data + case dataAdr(11 downto 10) is + when "00" => dataOut <= data1; + when "01" => dataOut <= data2; + when "10" => dataOut <= data3; + when others => dataOut <= data4; + end case; + end process; +end behavioral; diff --git a/src/registers.vhd b/src/registers.vhd new file mode 100644 index 0000000..da70df2 --- /dev/null +++ b/src/registers.vhd @@ -0,0 +1,59 @@ +-- registers.vhd +-- Created on: So 13. Nov 19:06:55 CET 2022 +-- Author(s): Alexander Graf, Carl Ries, Yannick Reiß +-- Content: Entity registers + +-------------------------------------------------------------- +-- important constants and types from riscv_types (LN 104ff.) +-- +-- constant reg_adr_size : integer := 5; +-- constant reg_size : integer := 32; +-- type regFile is array (reg_size - 1 downto 0) of word; +-------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.riscv_types.all; + +-- Entity registers: entity defining the pins and ports of the registerblock +entity registers is + generic (initRegs : regFile := (others => (others => '0'))); + port( + clk : in std_logic; -- input for clock (control device) + en_reg_wb : in one_bit; -- enable register write back (?) + data_in : in word; -- Data to be written into the register + wr_idx : in reg_idx; -- register to write to + r1_idx : in reg_idx; -- first register to read from + r2_idx : in reg_idx; -- second register to read from + write_enable : in one_bit; -- enable writing to wr_idx + r1_out : out word; -- data from first register + r2_out : out word; -- data from second register + led_out : out word -- output reg 2 to led + ); +end registers; + +-- Architecture structure of registers: read from two, write to one +architecture structure of registers is + signal registerbench : regFile := initRegs; +begin + + -- react only on clock changes + process (clk) -- runs only, when clk changed + begin + if rising_edge(clk) then + -- check if write is enabled + if to_integer(unsigned(write_enable)) = 1 then + -- write data_in to wr_idx + registerbench(to_integer(unsigned(wr_idx))) <= data_in; + end if; + registerbench(0) <= std_logic_vector(to_unsigned(0, wordWidth)); + end if; + end process; + -- read from both reading registers + r1_out <= registerbench(to_integer(unsigned(r1_idx))); + r2_out <= registerbench(to_integer(unsigned(r2_idx))); + led_out <= registerbench(2); + +end structure; diff --git a/src/riscv_types.vhd b/src/riscv_types.vhd new file mode 100755 index 0000000..ce0f1f6 --- /dev/null +++ b/src/riscv_types.vhd @@ -0,0 +1,136 @@ +-- riscv_types.vhd +-- Created on: So 13. Nov 19:05:44 CET 2022 +-- Author(s): Carl Ries, Yannick Reiß, Alexander Graf +-- Content: All types needed in processor +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package riscv_types is + + -- internal opCodes/enums for instructions + type uOP is (uNOP, uLUI, uAUIPC, uJAL, uJALR, uBEQ, uBNE, uBLT, uBGE, uBLTU, uBGEU, + uLB, uLH, uLW, uLBU, uLHU, uSB, uSH, uSW, uADDI, uSLTI, uSLTIU, + uXORI, uORI, uANDI, uSLLI, uSRLI, uSRAI, uADD, uSUB, uSLL, uSLT, + uSLTU, uXOR, uSRL, uSRA, uOR, uAND, uECALL); + + -- internal opCodes/enums for alu instructions + type aluOP is (uNOP, uADD, uSUB, uSLL, uSLT, uSLTU, uXOR, uSRL, uSRA, uOR, uAND); + + -- internal instruction formats + type inst_formats is (R, I, S, B, U, J); + + -- internal immediat formats + type imm_formats is (I, S, B, U, J); + + -- cpu states + type cpuStates is (stIF, stDEC, stOF, stEXEC, stWB); + + -- internal opCodes/enums for memory operation + type memOP is (uNOP, uLB, uLH, uLW, uLBU, uLHU, uSB, uSH, uSW); + + -- internal opCodes/enums for branching + type branchOP is (uNOP, uEQ, uNE, uLT, uLTU, uGE, uGEU); + + -- Size of words + constant wordWidth : integer := 32; + + -- bit vectors for different types + subtype word is std_logic_vector(wordWidth - 1 downto 0); -- 32bit (word) + subtype half is std_logic_vector(16 - 1 downto 0); -- 16bit (half) + subtype byte is std_logic_vector(8 - 1 downto 0); -- 8bit (byte) + subtype four_bit is std_logic_vector(4 - 1 downto 0); -- 4bit vector + subtype two_bit is std_logic_vector(2 - 1 downto 0); -- 2bit vector + subtype one_bit is std_logic_vector(1 - 1 downto 0); -- 1bit vector + subtype instruction is std_logic_vector(wordWidth - 1 downto 0); -- instruction + subtype opcode is std_logic_vector(7 - 1 downto 0); -- 7bit opcode + subtype reg_idx is std_logic_vector(5 - 1 downto 0); -- register index + subtype funct3 is std_logic_vector(3 - 1 downto 0); -- 3bit sub opcode + subtype shamt is std_logic_vector(5 - 1 downto 0); -- shift amount + subtype upper_imm is std_logic_vector(31 downto 12); -- upper immediate + subtype imm_12 is std_logic_vector(12 - 1 downto 0); -- 12bit immediate + + + -- constants for the 7bit opcode field in a normal 32bit instruction. + -- for 32bit size instructions the last 2 bits always have to be '1' + -- xxxxx11 + constant opc_LUI : opcode := "0110111"; -- load upper immediate + constant opc_AUIPC : opcode := "0010111"; -- add upper immediate to pc + constant opc_JAL : opcode := "1101111"; -- jump and link + constant opc_JALR : opcode := "1100111"; -- jump and link register + constant opc_BRANCH : opcode := "1100011"; -- branch -- + constant opc_LOAD : opcode := "0000011"; -- load -- + constant opc_STORE : opcode := "0100011"; -- store -- + constant opc_ALUI : opcode := "0010011"; -- alu immediate -- + constant opc_ALUR : opcode := "0110011"; -- alu register -- + constant opc_FENCE : opcode := "0001111"; -- fence + constant opc_ECALL : opcode := "1110011"; -- ecall + constant opc_EBREAK : opcode := "1110011"; -- break + constant opc_NULL : opcode := "0000000"; -- invalid + + -- constant for alu double funct3 entrys. (e.g. SUB instruction) + constant alu_flag : std_logic_vector(7 - 1 downto 0) := "0100000"; + + -- constants for the funct3 field on branches + constant branch_EQ : funct3 := "000"; + constant branch_NE : funct3 := "001"; + constant branch_LT : funct3 := "100"; + constant branch_GE : funct3 := "101"; + constant branch_LTU : funct3 := "110"; + constant branch_GEU : funct3 := "111"; + + -- constants for the funct3 field on loads + constant load_B : funct3 := "000"; -- byte + constant load_H : funct3 := "001"; -- half + constant load_W : funct3 := "010"; -- word + constant load_LBU : funct3 := "100"; -- byte unsigned + constant load_LHU : funct3 := "101"; -- half unsigned + + -- constants for the funct3 field on stores + constant store_B : funct3 := "000"; -- byte + constant store_H : funct3 := "001"; -- half + constant store_W : funct3 := "010"; -- word + + -- constants for the funct3 field for alu + constant alu_ADD : funct3 := "000"; -- add + constant alu_SUB : funct3 := "000"; -- sub also needs alu_flag set + constant alu_SLT : funct3 := "010"; -- set less than + constant alu_SLTU : funct3 := "011"; -- set less than immediate + constant alu_AND : funct3 := "111"; -- and + constant alu_OR : funct3 := "110"; -- or + constant alu_XOR : funct3 := "100"; -- xor + constant alu_SLL : funct3 := "001"; -- shift left logical + constant alu_SRL : funct3 := "101"; -- shift right logical + constant alu_SRA : funct3 := "101"; -- shift right arithmetic + +-- regFile constants and type + constant reg_adr_size : integer := 5; + constant reg_size : integer := 32; + type regFile is array (reg_size - 1 downto 0) of word; + + -- ram constants and type + constant ram_size : natural := 4096; + constant ram_block_size : natural := 1024; + constant ram_addr_size : natural := 12; + + subtype ram_addr_t is std_logic_vector(ram_addr_size -1 downto 0); + -- type ram_t is array(0 to ram_addr_size - 1) of word; + type ram_t is array(0 to 255) of word; + + -- const for multiplexer sources + constant mul_wr_alures : two_bit := "00"; + constant mul_wr_memread : two_bit := "01"; + constant mul_wr_pc4 : two_bit := "10"; + + constant mul_alu_reg : one_bit := "0"; + + constant mul_alu_pc : one_bit := "1"; + constant mul_alu_imm : one_bit := "1"; + + constant mul_pc_pc4 : one_bit := "0"; + constant mul_pc_alu : one_bit := "1"; + +end riscv_types; + +package body riscv_types is +end riscv_types; diff --git a/tb/tb_alu.vhd b/tb/tb_alu.vhd new file mode 100644 index 0000000..ee46c4e --- /dev/null +++ b/tb/tb_alu.vhd @@ -0,0 +1,263 @@ +-- tb_alu.vhd +-- Created on: Mo 21. Nov 11:21:12 CET 2022 +-- Author(s): Carl Ries, Yannick Reiß, Alexander Graf +-- Content: Testbench for ALU +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.uniform; +use ieee.math_real.floor; + +library work; +use work.riscv_types.all; + +library std; +use std.textio.all; + +-- Entity alu_tb: dummy entity +entity alu_tb is +end alu_tb; + +-- Architecture testing of alu_tb: testing calculations +architecture testing of alu_tb is + -- clock definition + signal clk : std_logic; + constant clk_period : time := 10 ns; + + -- Inputs + signal alu_opc_tb : aluOP; + signal input1_tb : word; + signal input2_tb : word; + + -- Outputs + signal result_tb : word; + + -- unittest signals + signal random_slv : word; + signal check_slt : word; + signal check_sltu : word; + signal rand_num : integer := 0; + + -- function for random_std_logic_vector + impure function get_random_slv return std_logic_vector is + + -- random number variabeln + variable seed1 : integer := 1337; + variable seed2 : integer := rand_num; --Zufallszahl + variable r : real; + variable slv : std_logic_vector(wordWidth - 1 downto 0); + + begin + for i in slv'range loop + uniform(seed1, seed2, r); + seed1 := seed1 + 2; + end loop; + seed2 := seed2 + 2; + return slv; + end function get_random_slv; + +begin + -- Entity work.alu(implementation): Init of Unit Under Test + uut : entity work.alu(implementation) + port map ( + alu_opc => alu_opc_tb, + input1 => input1_tb, + input2 => input2_tb, + result => result_tb + ); + + + -- Process Random Integer + rand_process : process -- Prozess um einen Zufälligen Integer zu generieren + + variable seed1, seed2 : positive; -- Startwert der Zufallszahl + variable rand : real; -- Zufallszahl zwischen 0 und 1 + variable range_of_rand : real := 10000.0; -- Die Range wird auf 10000 festgelegt + + begin + uniform(seed1, seed2, rand); -- Generiert Zufallszahl + rand_num <= integer(rand*range_of_rand); -- Zahl wird zwischen 0 und range_of_rand skaliert + wait for 10 ns; + end process; + + + -- Process clk_process operating the clock + clk_process : process -- runs only, when changed + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + -- Process stim_proc control device for uut + stim_proc : process -- runs only, when changed + -- Text I/O + variable lineBuffer : line; + begin + -- wait for the rising edge + wait until rising_edge(clk); + + -- Print the top element + write(lineBuffer, string'("Start the simulator")); + writeline(output, lineBuffer); + + -- For schleife für 20 Testdurchläufe + for i in 1 to 20 loop + + --create example inputs + input1_tb <= std_logic_vector( to_unsigned(10, 32) ); + wait for 10 ns; + input2_tb <= std_logic_vector( to_unsigned(7, 32) ); + alu_opc_tb <= uNop; + wait for 10 ns; + + -- Ausgabe input1_tb und input2_tb + -- Dient zur Kontrolle das zufällige Zahlen ausgegeben werden. + write(lineBuffer, string'("Zufahlszahl 1: ")); + + write(lineBuffer, string'("Zufahlszahl 2: ")); + + -- NOP + if (unsigned(result_tb) = 0) then + write(lineBuffer, string'("NOP: +")); + writeline(output, lineBuffer); + else + write(lineBuffer, string'("NOP: -")); + writeline(output, lineBuffer); + end if; + alu_opc_tb <= uADD; + wait for 10 ns; + + -- ADD + if (unsigned(result_tb) = unsigned(input1_tb) + unsigned(input2_tb)) then + write(lineBuffer, string'("ADD: +")); + writeline(output, lineBuffer); + else + write(lineBuffer, string'("ADD: -")); + writeline(output, lineBuffer); + end if; + alu_opc_tb <= uSUB; + wait for 10 ns; + + -- SUB + if (unsigned(result_tb) = unsigned(input1_tb) - unsigned(input2_tb)) then + write(lineBuffer, string'("SUB: +")); + writeline(output, lineBuffer); + else + write(lineBuffer, string'("SUB: -")); + writeline(output, lineBuffer); + end if; + alu_opc_tb <= uSLL; + wait for 10 ns; + + -- SLL + if (unsigned(result_tb) = (unsigned(input1_tb) sll 1)) then + write(lineBuffer, string'("SLL: +")); + writeline(output, lineBuffer); + else + write(lineBuffer, string'("SLL: -")); + writeline(output, lineBuffer); + end if; + alu_opc_tb <= uSLT; + wait for 10 ns; + + -- SLT + if(signed(input1_tb) < signed(input2_tb)) then + check_slt <= std_logic_vector(to_unsigned(1, wordWidth)); + else + check_slt <= std_logic_vector(to_unsigned(0, wordWidth)); + end if; -- Set lower than + wait for 10 ns; + if (result_tb = check_slt) then + write(lineBuffer, string'("SLT: +")); + writeline(output, lineBuffer); + else + write(lineBuffer, string'("SLT: -")); + writeline(output, lineBuffer); + end if; + alu_opc_tb <= uSLTU; + wait for 10 ns; + + -- SLTU + if(unsigned(input1_tb) < unsigned(input2_tb)) then + check_sltu <= std_logic_vector(to_unsigned(1, wordWidth)); + else + check_sltu <= std_logic_vector(to_unsigned(0, wordWidth)); + end if; -- Set lower than unsigned + wait for 10 ns; + if (result_tb = check_sltu) then + write(lineBuffer, string'("SLTU: +")); + writeline(output, lineBuffer); + else + write(lineBuffer, string'("SLTU: -")); + writeline(output, lineBuffer); + end if; + alu_opc_tb <= uXOR; + wait for 10 ns; + + -- XOR + if (result_tb = (input1_tb xor input2_tb)) then + write(lineBuffer, string'("XOR: +")); + writeline(output, lineBuffer); + else + write(lineBuffer, string'("XOR: -")); + writeline(output, lineBuffer); + end if; + alu_opc_tb <= uSRL; + wait for 10 ns; + + -- SRL + if (unsigned(result_tb) = (unsigned(input1_tb) srl 1)) then + write(lineBuffer, string'("SRL: +")); + writeline(output, lineBuffer); + else + write(lineBuffer, string'("SRL: -")); + writeline(output, lineBuffer); + end if; + alu_opc_tb <= uSRA; + wait for 10 ns; + + -- SRA + if (unsigned(result_tb) = unsigned(std_logic_vector(to_stdlogicvector(to_bitvector(input1_tb) sra 1)))) then + write(lineBuffer, string'("SRA: +")); + writeline(output, lineBuffer); + else + write(lineBuffer, string'("SRA: -")); + writeline(output, lineBuffer); + end if; + alu_opc_tb <= uOR; + wait for 10 ns; + + -- OR + if (result_tb = (input1_tb or input2_tb)) then + write(lineBuffer, string'("OR: +")); + writeline(output, lineBuffer); + else + write(lineBuffer, string'("OR: -")); + writeline(output, lineBuffer); + end if; + alu_opc_tb <= uAND; + wait for 10 ns; + + -- AND + if (result_tb = (input1_tb and input2_tb)) then + write(lineBuffer, string'("AND: +")); + writeline(output, lineBuffer); + else + write(lineBuffer, string'("AND: -")); + writeline(output, lineBuffer); + end if; + + -- end loop + end loop; + + -- end simulation + write(lineBuffer, string'("end of simulation")); + writeline(output, lineBuffer); + + -- I'm still waiting + wait; + end process; +end testing; + diff --git a/tb/tb_cpu.vhd b/tb/tb_cpu.vhd new file mode 100644 index 0000000..9d5a208 --- /dev/null +++ b/tb/tb_cpu.vhd @@ -0,0 +1,49 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.riscv_types.all; + +library std; +use std.textio.all; + +entity cpu_tb is +end cpu_tb; + +architecture Behavioral of cpu_tb is + + -- Clock + signal clk : std_logic; + + -- Inputs + + -- Outputs + -- Clock period definitions + constant clk_period : time := 10 ns; + +begin + + -- Instantiate the Unit Under Test (UUT) + uut : entity work.cpu(implementation) + port map (clk => clk); + + -- Clock process definitions + clk_process : process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + -- Process stim_proc stimulate uut + stim_proc : process -- runs only, when changed + variable lineBuffer : line; + begin + write(lineBuffer, string'("Start the simulator")); + writeline(output, lineBuffer); + + wait; + end process; +end architecture; diff --git a/tb/tb_decoder.vhd b/tb/tb_decoder.vhd new file mode 100644 index 0000000..ed7d77f --- /dev/null +++ b/tb/tb_decoder.vhd @@ -0,0 +1,84 @@ +-- tb_decoder.vhd +-- Created on: Di 6. Dez 10:50:02 CET 2022 +-- Author(s): Yannick Reiß, Car Ries, Alexander Graf +-- Content: Testbench for decoder (NOT AUTOMATED, ONLY STIMULI) + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.uniform; + +library work; +use work.riscv_types.all; + +library std; +use std.textio.all; + +-- Entity decoder_tb: dummy entity for decoder +entity decoder_tb is +end decoder_tb; + +-- Architecture testingdecoder of decoder_tb: testing instruction decode +architecture testingdecoder of decoder_tb is + -- clk + signal clk : std_logic; + constant clk_period : time := 10 ns; + + -- inputs + signal instrDecode : instruction; + + -- outputs + signal aluOpCode : uOP; + signal regOp1 : reg_idx; + signal regOp2 : reg_idx; + signal regWrite : reg_idx; +begin + uut : entity work.decoder(decode) + port map ( + instrDecode => instrDecode, + op_code => aluOpCode, + regOp1 => regOp1, + regOp2 => regOp2, + regWrite => regWrite); + + -- clk-prog + clk_process : process -- runs only, when changed + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + -- Process stim_proc stimulate uut + stim_proc : process -- runs only, when changed + variable lineBuffer : line; + begin + write(lineBuffer, string'("Start the simulator")); + writeline(output, lineBuffer); + + wait for 5 ns; + + -- add x9, x0, x3 + instrDecode <= "00000000001100000000010010110011"; + wait for 10 ns; + + -- add x1, x2, x3 + instrDecode <= "00000000001100010000000010110011"; + wait for 10 ns; + + -- sll x1, x0, x2 + instrDecode <= "00000000001000000001000010110011"; + wait for 10 ns; + + -- sub x6, x3, x1 + instrDecode <= "01000000000100011000001100110011"; + wait for 10 ns; + + -- nop x6, x3, x1 + instrDecode <= "01000000000100011000001100110111"; + wait for 10 ns; + + wait; + end process; +end testingdecoder; diff --git a/tb/tb_imm.vhd b/tb/tb_imm.vhd new file mode 100644 index 0000000..83dafbf --- /dev/null +++ b/tb/tb_imm.vhd @@ -0,0 +1,77 @@ +-- tb_imm.vhd +-- Created on: Tu 10. Jan 21:10:00 CET 2023 +-- Author(s): Yannick Reiß +-- Content: testbench for immediate entity +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library work; +use work.riscv_types.all; + +library std; +use std.textio.all; + +-- Entity imm_tb: dummy entity + entity imm_tb is + end imm_tb; + +architecture testing of imm_tb is + + -- clock definition + signal clk : std_logic; + constant clk_period : time := 10 ns; + + -- inputs imm + signal s_instruction : instruction; + signal s_opcode : uOP; + + -- outputs imm + signal s_immediate : word; + +begin + uut : entity work.imm + port map( + + instruction => s_instruction, + opcode => s_opcode, + immediate => s_immediate + ); + + -- Process clk_process operating the clock + clk_process : process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + -- stimulation process + stim_proc : process + variable lineBuffer : line; + begin + -- wait for the rising edge + wait until rising_edge(clk); + + wait for 10 ns; + + write(lineBuffer, string'("Start the simulator")); + writeline(output, lineBuffer); + + -- testcases + -- addi x3, x0, 5 + s_instruction <= x"00500193"; + s_opcode <= uADDI; + + wait for 10 ns; + + -- addi x2, x0, 1 + s_instruction <= x"00100113"; + s_opcode <= uADDI; + + wait; + + end process; + +end architecture; -- testing diff --git a/tb/tb_pc.vhd b/tb/tb_pc.vhd new file mode 100644 index 0000000..0ec38b6 --- /dev/null +++ b/tb/tb_pc.vhd @@ -0,0 +1,133 @@ +-- tb_pc.vhd +-- Created on: Mo 05. Dec 15:44:55 CET 2022 +-- Author(s): Carl Ries, Yannick Reiß, Alexander Graf +-- Content: Testbench for program counter +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.riscv_types.all; + +library std; +use std.textio.all; + +-- Entity pc_tb: dummy entity +entity pc_tb is +end pc_tb; + +-- Architecture testing of pc_tb: testing calculations +architecture testing of pc_tb is + -- clock definition + signal clk : std_logic; + constant clk_period : time := 10 ns; + + -- Inputs pc + signal en_pc : one_bit; + signal addr_calc : ram_addr_t; + signal doJump : one_bit; + + -- Outputs pc + signal addr : ram_addr_t; + + -- unittest signals pc + signal addr_calc_tb : ram_addr_t; + +begin + -- Entity work.pc(pro_count): Init of Unit Under Test + uut1 : entity work.pc + port map ( + clk => clk, + en_pc => en_pc, + addr_calc => addr_calc, + doJump => doJump, + addr => addr + ); + + -- Process clk_process operating the clock + clk_process : process -- runs only, when changed + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + -- Process stim_proc control device for uut + stim_proc : process -- runs only, when changed + -- Text I/O + variable lineBuffer : line; + begin + + -- wait for the rising edge + wait until rising_edge(clk); + + wait for 10 ns; + + -- Print the top element + write(lineBuffer, string'("Start the simulator")); + writeline(output, lineBuffer); + + -- testcases + + -- Case 1: addr_calc + write(lineBuffer, string'("Testing Case 1: ")); + writeline(output, lineBuffer); + + en_pc <= std_logic_vector(to_unsigned(1, 1)); + doJump <= std_logic_vector(to_unsigned(1, 1)); + addr_calc <= std_logic_vector(to_unsigned(30, ram_addr_size)); + wait for 10 ns; + + if addr = std_logic_vector(to_unsigned(30, ram_addr_size)) then + write(lineBuffer, string'("Result 1: +")); + writeline(output, lineBuffer); + else + write(lineBuffer, string'("Result 1: -")); + writeline(output, lineBuffer); + end if; + + -- Case 2: count + write(lineBuffer, string'("Testing Case 2: ")); + writeline(output, lineBuffer); + + en_pc <= std_logic_vector(to_unsigned(1, 1)); + doJump <= std_logic_vector(to_unsigned(0, 1)); + addr_calc <= std_logic_vector(to_unsigned(60, ram_addr_size)); + wait for 10 ns; + + --same value from + if addr = std_logic_vector(to_unsigned(31, ram_addr_size)) then + write(lineBuffer, string'("Result 2: +")); + writeline(output, lineBuffer); + else + write(lineBuffer, string'("Result 2: -")); + writeline(output, lineBuffer); + end if; + + -- Case 3: hold + write(lineBuffer, string'("Testing Case 3: ")); + writeline(output, lineBuffer); + + en_pc <= std_logic_vector(to_unsigned(0, 1)); + doJump <= std_logic_vector(to_unsigned(0, 1)); + addr_calc <= std_logic_vector(to_unsigned(90, ram_addr_size)); + wait for 10 ns; + + --same value from + if addr = std_logic_vector(to_unsigned(31, ram_addr_size)) then + write(lineBuffer, string'("Result 3: +")); + writeline(output, lineBuffer); + else + write(lineBuffer, string'("Result 3: -")); + writeline(output, lineBuffer); + end if; + + -- I'm still waiting + wait; + end process; +end testing; + + + + diff --git a/tb/tb_ram.vhd b/tb/tb_ram.vhd new file mode 100644 index 0000000..4c2f410 --- /dev/null +++ b/tb/tb_ram.vhd @@ -0,0 +1,106 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.riscv_types.all; + +library std; +use std.textio.all; + +entity ram_tb is +end ram_tb; + +architecture Behavioral of ram_tb is + + -- Clock + signal clk : std_logic; + + -- Inputs + signal addr_a : std_logic_vector(ram_addr_size - 1 downto 0); + signal write_b : std_logic_vector(1-1 downto 0); + signal addr_b : std_logic_vector(ram_addr_size - 1 downto 0); + signal data_write_b : std_logic_vector(wordWidth - 1 downto 0); + + -- Outputs + signal data_read_a : std_logic_vector(wordWidth - 1 downto 0); + signal data_read_b : std_logic_vector(wordWidth - 1 downto 0); + + -- Clock period definitions + constant clk_period : time := 10 ns; + + -- Unittest Signale + signal tb_addr_a : integer; + signal tb_addr_b : integer; + signal tb_test_v : std_logic_vector(wordWidth - 1 downto 0); + signal tb_check_v : std_logic_vector(wordWidth - 1 downto 0); + signal tb_validate : std_logic; + +begin + + -- Instantiate the Unit Under Test (UUT) + uut : entity work.ram(Behavioral) + port map (clk => clk, + instructionAdr => addr_a, + dataAdr => addr_b, + writeEnable => write_b, + dataIn => data_write_b, + instruction => data_read_a, + dataOut => data_read_b); + + -- Clock process definitions + clk_process : process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + -- Stimulus process + stim_proc : process + variable lineBuffer : line; + begin + + wait for 5 ns; + + -- Wait for the first rising edge + wait until rising_edge(clk); + + -- manual test + addr_a <= "001101001110"; + addr_b <= "011100110010"; + write_b <= "1"; + + wait for 10 ns; + + -- Testing Mem + tb_validate <= '1'; + write_b <= std_logic_vector(to_unsigned(1, 1)); + for test_case in 0 to 1000 loop + for tb_addr in 0 to 4096 loop + -- assign test values + tb_test_v <= std_logic_vector(to_unsigned(tb_addr, wordWidth)); + tb_check_v <= std_logic_vector(to_unsigned(tb_addr, wordWidth)); + + -- Test this value + addr_a <= std_logic_vector(to_unsigned(tb_addr, ram_addr_size)); + addr_b <= std_logic_vector(to_unsigned(tb_addr, ram_addr_size)); + data_write_b <= tb_test_v; + + if (data_read_a = tb_check_v and data_read_b = tb_check_v) then + tb_validate <= '0'; + write(lineBuffer, string'("Everything fine!")); + writeline(output, lineBuffer); + else + tb_validate <= '1'; + end if; + wait for 10 ns; + end loop; + end loop; + + -- Simply wait forever + wait; + + end process; +end architecture; diff --git a/tb/tb_reg.vhd b/tb/tb_reg.vhd new file mode 100644 index 0000000..25d70ae --- /dev/null +++ b/tb/tb_reg.vhd @@ -0,0 +1,231 @@ +-- tb_reg.vhd +-- Created on: Mo 14. Nov 11:55:58 CET 2022 +-- Author(s): Yannick Reiß, Alexander Graf, Carl Ries +-- Content: Testbench for the registerblock + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.uniform; + +library work; +use work.riscv_types.all; + +library std; +use std.textio.all; + +-- Entity regs_tb: Entity providing testinputs, receiving testoutputs for registerbench +entity regs_tb is +end regs_tb; + +-- Architecture testing of regs_tb: testing read / write operations +architecture testing of regs_tb is + -- clock definition + signal clk : std_logic; + constant clk_period : time := 10 ns; + + -- Inputs + signal en_reg_wb_tb : one_bit; + signal data_in_tb : word; + signal wr_idx_tb : reg_idx; + signal r1_idx_tb : reg_idx; + signal r2_idx_tb : reg_idx; + signal write_enable_tb : one_bit; + + -- Outputs + signal r1_out_tb : word; + signal r2_out_tb : word; + + -- unittest signals + signal random_slv: word; + + --function for random_std_logic_vector + function get_random_slv return std_logic_vector is + + -- random number variablen + variable seed1 : integer := 1; + variable seed2 : integer := 1; + variable r : real; + variable slv : std_logic_vector(wordWidth - 1 downto 0); + + begin + for i in slv'range loop + uniform(seed1, seed2, r); + slv(i) := '1' when r > 0.5 else '0'; + end loop; + return slv; + end function; + +begin + + -- Init of Unit Under Test + uut : entity work.registers(Structure) + port map ( + clk => clk, + en_reg_wb => en_reg_wb_tb, + data_in => data_in_tb, + wr_idx => wr_idx_tb, + r1_idx => r1_idx_tb, + r2_idx => r2_idx_tb, + write_enable => write_enable_tb, + r1_out => r1_out_tb, + r2_out => r2_out_tb + ); + + -- Process clk_process operating the clock + clk_process : process -- runs always + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + -- Stimulating the UUT + -- Process stim_proc control device for + stim_proc : process + -- Text I/O + variable lineBuffer : line; + + begin + + -- wait for the rising edge + wait until rising_edge(clk); + + wait for 5 ns; + + -- Print the top element + write(lineBuffer, string'("Start the simulation: ")); + writeline(output, lineBuffer); + + -- set the stimuli here + + -- Case 1: write to x=7 + read x=4 + write(lineBuffer, string'("Testing Case 1: ")); + writeline(output, lineBuffer); + + write_enable_tb <= std_logic_vector(to_unsigned(1, 1)); + data_in_tb<= std_logic_vector(to_unsigned(7, wordWidth)); + wr_idx_tb <= std_logic_vector(to_unsigned(7, reg_adr_size)); + r1_idx_tb <= std_logic_vector(to_unsigned(4, reg_adr_size)); + r2_idx_tb <= std_logic_vector(to_unsigned(7, reg_adr_size)); + wait for 10 ns; + + if r1_out_tb = std_logic_vector(to_unsigned(0, wordWidth)) and r2_out_tb = std_logic_vector(to_unsigned(7, wordWidth)) then + write(lineBuffer, string'("Result 1: +")); + writeline(output, lineBuffer); + else + write(lineBuffer, string'("Result 1: -")); + writeline(output, lineBuffer); + end if; + + -- Case 2: write to x=27 + read x=0 + write(lineBuffer, string'("Testing Case 2: ")); + writeline(output, lineBuffer); + + write_enable_tb <= std_logic_vector(to_unsigned(1, 1)); + data_in_tb<= std_logic_vector(to_unsigned(7, wordWidth)); + wr_idx_tb <= std_logic_vector(to_unsigned(27, reg_adr_size)); + r1_idx_tb <= std_logic_vector(to_unsigned(0, reg_adr_size)); + r2_idx_tb <= std_logic_vector(to_unsigned(27, reg_adr_size)); + wait for 10 ns; + + if r1_out_tb = std_logic_vector(to_unsigned(0, wordWidth)) and r2_out_tb = std_logic_vector(to_unsigned(7, wordWidth)) then + write(lineBuffer, string'("Result 2: +")); + writeline(output, lineBuffer); + else + write(lineBuffer, string'("Result 2: -")); + writeline(output, lineBuffer); + end if; + + -- Case 3: write to zero + read from zero x2 + write(lineBuffer, string'("Testing Case 3: ")); + writeline(output, lineBuffer); + + write_enable_tb <= std_logic_vector(to_unsigned(1, 1)); + data_in_tb<= std_logic_vector(to_unsigned(7, wordWidth)); + wr_idx_tb <= std_logic_vector(to_unsigned(0, reg_adr_size)); + r1_idx_tb <= std_logic_vector(to_unsigned(0, reg_adr_size)); + r2_idx_tb <= std_logic_vector(to_unsigned(27, reg_adr_size)); + wait for 10 ns; + + if r1_out_tb = std_logic_vector(to_unsigned(0, wordWidth)) then + write(lineBuffer, string'("Result 3: +")); + writeline(output, lineBuffer); + else + write(lineBuffer, string'("Result 3: -")); + writeline(output, lineBuffer); + end if; + + -- Case 4: write to 31 + read from 31 + write(lineBuffer, string'("Testing Case 4: ")); + writeline(output, lineBuffer); + + write_enable_tb <= std_logic_vector(to_unsigned(1, 1)); + data_in_tb<= std_logic_vector(to_unsigned(7, wordWidth)); + wr_idx_tb <= std_logic_vector(to_unsigned(31, reg_adr_size)); + r1_idx_tb <= std_logic_vector(to_unsigned(31, reg_adr_size)); + r2_idx_tb <= std_logic_vector(to_unsigned(0, reg_adr_size)); + wait for 10 ns; + + if r1_out_tb = std_logic_vector(to_unsigned(7, wordWidth)) then + write(lineBuffer, string'("Result 4: +")); + writeline(output, lineBuffer); + else + write(lineBuffer, string'("Result 4: -")); + writeline(output, lineBuffer); + end if; + + -- Case 5: read x=7 + read x=18 + write(lineBuffer, string'("Testing Case 5: ")); + writeline(output, lineBuffer); + + write_enable_tb <= std_logic_vector(to_unsigned(0, 1)); + data_in_tb<= std_logic_vector(to_unsigned(9, wordWidth)); + wr_idx_tb <= std_logic_vector(to_unsigned(7, reg_adr_size)); + r1_idx_tb <= std_logic_vector(to_unsigned(7, reg_adr_size)); + r2_idx_tb <= std_logic_vector(to_unsigned(18, reg_adr_size)); + wait for 10 ns; + + -- Not allowed to change, last value was 7, new "would" be 9 + if r1_out_tb = std_logic_vector(to_unsigned(7, wordWidth)) then + write(lineBuffer, string'("Result 5: +")); + writeline(output, lineBuffer); + else + write(lineBuffer, string'("Result 5: -")); + writeline(output, lineBuffer); + end if; + + -- Case 6: RANDOM_Test write to 12 + read from 12 + write(lineBuffer, string'("Testing Case 6: ")); + writeline(output, lineBuffer); + + -- get random_logic_vector + random_slv <= get_random_slv; + + wait for 10 ns; + + write_enable_tb <= std_logic_vector(to_unsigned(1, 1)); + data_in_tb <= random_slv; + wr_idx_tb <= std_logic_vector(to_unsigned(12, reg_adr_size)); + r1_idx_tb <= std_logic_vector(to_unsigned(12, reg_adr_size)); + r2_idx_tb <= std_logic_vector(to_unsigned(0, reg_adr_size)); + wait for 10 ns; + + if r1_out_tb = random_slv then + write(lineBuffer, string'("Result 6: +")); + writeline(output, lineBuffer); + else + write(lineBuffer, string'("Result 6: -")); + writeline(output, lineBuffer); + end if; + + -- end simulation + write(lineBuffer, string'("end of simulation")); + writeline(output, lineBuffer); + + -- I'm still waiting + wait; + end process; + +end testing;