Implement reset of the processor

.gitignore

@@ -3,3 +3,4 @@
 *.cf
 xvhdl*
 Vivado*
+*_tb

src/cpu.vhd

@@ -29,6 +29,7 @@ architecture implementation of cpu is
   component pc
     port(
       clk       : in  std_logic;        -- Clock input for timing
+      reset     : in  std_logic;
       en_pc     : in  one_bit;          -- activates PC
       addr_calc : in  ram_addr_t;       -- Address from ALU
       doJump    : in  one_bit;          -- Jump to Address
@@ -66,6 +67,7 @@ architecture implementation of cpu is
   component registers
     port(
       clk          : in  std_logic;     -- input for clock (control device)
+      reset        : in  std_logic;
       en_reg_wb    : in  one_bit;       -- enable register write back (?)
       data_in      : in  word;          -- Data to be written into the register
       wr_idx       : in  reg_idx;       -- register to write to
@@ -133,8 +135,8 @@ architecture implementation of cpu is
   signal X_addr_calc : ram_addr_t;
 
   -- Clock signals
-  signal reset  : std_logic;
+  signal reset  : std_logic := '0';
-  signal locked : std_logic;
+  signal locked : std_logic := '0';
 
 -------------------------
 -- additional ALU signals
@@ -151,6 +153,7 @@ begin
 
   -- External assignments
   s_clock             <= clk;
+  reset               <= rst;
   ram_enable_writing  <= s_ram_enable;
   instruction_pointer <= s_instAddr;
   data_address        <= s_data_in_addr;
@@ -170,6 +173,7 @@ begin
   registers_RISCV : registers
     port map(
       clk          => s_clock,
+      reset        => reset,
       en_reg_wb    => s_reg_wb_enable,
       data_in      => reg_data_in,
       wr_idx       => s_idx_wr,
@@ -190,6 +194,7 @@ begin
   pc_RISCV : pc
     port map(
       clk       => s_clock,
+      reset     => reset,
       en_pc     => s_pc_enable,
       addr_calc => X_addr_calc,
       doJump    => s_pc_jump_enable,
@@ -243,7 +248,6 @@ begin
       when others => aluIn1 <= s_reg_data1;
     end case;
 
-    -- TODO: why line from pc to alu inp1?
     -- connect input 2
     case s_opcode is
       when uADDI | uSLTI | uSLTIU | uXORI | uORI | uANDI => aluIn2 <= s_immediate;
@@ -313,7 +317,7 @@ begin
   end process;
 
   -- pc cycle control
-  pc_cycle_control : process(s_clock)
+  pc_cycle_control : process(s_clock, reset)
   begin
     if rising_edge(s_clock) then
       case s_cycle_cnt is
@@ -323,6 +327,10 @@ begin
         when stEXEC => s_cycle_cnt <= stWB;
         when others => s_cycle_cnt <= stIF;
       end case;
+    else
+      if falling_edge(reset) then
+        s_cycle_cnt <= stIF;
+      end if;
     end if;
   end process pc_cycle_control;
 

src/pc.vhd

@@ -12,6 +12,7 @@ use work.riscv_types.all;
 -- Entity PC: entity defining the pins and ports of the programmcounter
 entity pc is
   port (clk       : in  std_logic;      -- Clock input for timing
+        reset     : in  std_logic;
         en_pc     : in  one_bit;        -- activates PC
         addr_calc : in  ram_addr_t;     -- Address from ALU
         doJump    : in  one_bit;        -- Jump to Address
@@ -40,6 +41,14 @@ begin
     end if;
   end process;
 
+  process (reset)
+  begin
+    if falling_edge(reset) then
+      addr_out      <= (others => '0');
+      addr_out_plus <= (others => '0');
+    end if;
+  end process;
+
   addr_out_plus <= (std_logic_vector(to_unsigned(to_integer(unsigned(addr_out)) + 4, ram_addr_size)));
   addr          <= addr_out;
 

src/registers.vhd

@@ -22,6 +22,7 @@ entity registers is
     generic (initRegs : regFile := (others => (others => '0')));
     port(
         clk          : in  std_logic;   -- input for clock (control device)
+        reset        : in  std_logic;
         en_reg_wb    : in  one_bit;     -- enable register write back (?)
         data_in      : in  word;        -- Data to be written into the register
         wr_idx       : in  reg_idx;     -- register to write to
@@ -50,6 +51,15 @@ begin
             registerbench(0) <= std_logic_vector(to_unsigned(0, wordWidth));
         end if;
     end process;
+
+    -- reset if reset is activated
+    process (reset)
+    begin
+        if falling_edge(reset) then
+            registerbench <= initRegs;
+        end if;
+    end process;
+
     -- read from both reading registers
     r1_out <= registerbench(to_integer(unsigned(r1_idx)));
     r2_out <= registerbench(to_integer(unsigned(r2_idx)));

tb/tb_cpu.vhd

@@ -13,11 +13,9 @@ end cpu_tb;
 
 architecture Behavioral of cpu_tb is
 
-  -- Clock
+  -- Clock and Reset
   signal clk : std_logic;
 
-  -- Inputs
-
   -- Outputs
   -- Clock period definitions
   constant clk_period : time := 10 ns;
@@ -76,6 +74,11 @@ begin
     write(lineBuffer, string'("Start the simulator"));
     writeline(output, lineBuffer);
 
+    wait for 100 ns;
+    cpu_reset <= '1';
+    wait for 17 ns;
+    cpu_reset <= '0';
+
     wait;
   end process;
 end architecture;

tb/tb_pc.vhd

@@ -33,11 +33,14 @@ architecture testing of pc_tb is
     -- unittest signals pc
     signal addr_calc_tb : ram_addr_t;
 
+    signal reset : std_logic;
+
 begin
     -- Entity work.pc(pro_count): Init of Unit Under Test
     uut1 : entity work.pc
         port map (
             clk       => clk,
+            reset     => reset,
             en_pc     => en_pc,
             addr_calc => addr_calc,
             doJump    => doJump,

tb/tb_reg.vhd

@@ -37,7 +37,9 @@ architecture testing of regs_tb is
     signal r2_out_tb : word;
 
     -- unittest signals
-	signal random_slv: word;
+    signal random_slv : word;
+
+    signal reset : std_logic;
 
     --function for random_std_logic_vector
     function get_random_slv return std_logic_vector is
@@ -62,6 +64,7 @@ begin
     uut : entity work.registers(Structure)
         port map (
             clk          => clk,
+            reset        => reset,
             en_reg_wb    => en_reg_wb_tb,
             data_in      => data_in_tb,
             wr_idx       => wr_idx_tb,
@@ -105,7 +108,7 @@ begin
         writeline(output, lineBuffer);
 
         write_enable_tb <= std_logic_vector(to_unsigned(1, 1));
-		data_in_tb<= std_logic_vector(to_unsigned(7, wordWidth));
+        data_in_tb      <= std_logic_vector(to_unsigned(7, wordWidth));
         wr_idx_tb       <= std_logic_vector(to_unsigned(7, reg_adr_size));
         r1_idx_tb       <= std_logic_vector(to_unsigned(4, reg_adr_size));
         r2_idx_tb       <= std_logic_vector(to_unsigned(7, reg_adr_size));
@@ -124,7 +127,7 @@ begin
         writeline(output, lineBuffer);
 
         write_enable_tb <= std_logic_vector(to_unsigned(1, 1));
-		data_in_tb<= std_logic_vector(to_unsigned(7, wordWidth));
+        data_in_tb      <= std_logic_vector(to_unsigned(7, wordWidth));
         wr_idx_tb       <= std_logic_vector(to_unsigned(27, reg_adr_size));
         r1_idx_tb       <= std_logic_vector(to_unsigned(0, reg_adr_size));
         r2_idx_tb       <= std_logic_vector(to_unsigned(27, reg_adr_size));
@@ -143,7 +146,7 @@ begin
         writeline(output, lineBuffer);
 
         write_enable_tb <= std_logic_vector(to_unsigned(1, 1));
-		data_in_tb<= std_logic_vector(to_unsigned(7, wordWidth));
+        data_in_tb      <= std_logic_vector(to_unsigned(7, wordWidth));
         wr_idx_tb       <= std_logic_vector(to_unsigned(0, reg_adr_size));
         r1_idx_tb       <= std_logic_vector(to_unsigned(0, reg_adr_size));
         r2_idx_tb       <= std_logic_vector(to_unsigned(27, reg_adr_size));
@@ -162,7 +165,7 @@ begin
         writeline(output, lineBuffer);
 
         write_enable_tb <= std_logic_vector(to_unsigned(1, 1));
-		data_in_tb<= std_logic_vector(to_unsigned(7, wordWidth));
+        data_in_tb      <= std_logic_vector(to_unsigned(7, wordWidth));
         wr_idx_tb       <= std_logic_vector(to_unsigned(31, reg_adr_size));
         r1_idx_tb       <= std_logic_vector(to_unsigned(31, reg_adr_size));
         r2_idx_tb       <= std_logic_vector(to_unsigned(0, reg_adr_size));
@@ -181,7 +184,7 @@ begin
         writeline(output, lineBuffer);
 
         write_enable_tb <= std_logic_vector(to_unsigned(0, 1));
-		data_in_tb<= std_logic_vector(to_unsigned(9, wordWidth));
+        data_in_tb      <= std_logic_vector(to_unsigned(9, wordWidth));
         wr_idx_tb       <= std_logic_vector(to_unsigned(7, reg_adr_size));
         r1_idx_tb       <= std_logic_vector(to_unsigned(7, reg_adr_size));
         r2_idx_tb       <= std_logic_vector(to_unsigned(18, reg_adr_size));