yannickreiss
/
RISCV
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Compare commits

base: yannickreiss:1772ac2af22ba6ca758082b7f65a36d6e96df05b
Branches Tags
yannickreiss:main
..
compare: yannickreiss:83c663241555a774768213fe456630ec34a31c35
Branches Tags
yannickreiss:main

2 Commits
1772ac2af2 ... 83c6632415

Author SHA1 Message Date
Yannick Reiß 83c6632415
Implement reset of the processor 2024-08-08 06:05:54 +02:00
Yannick Reiß f4316f565e
add compiled modules to gitignore 2024-08-07 18:56:31 +02:00
7 changed files with 344 additions and 307 deletions
Show Stats Expand all files Collapse all files

1
.gitignore vendored
View File

@ -3,3 +3,4 @@
*.cf *.cf
xvhdl* xvhdl*
Vivado* Vivado*
*_tb

16
src/cpu.vhd
View File

@ -29,6 +29,7 @@ architecture implementation of cpu is
component pc component pc
port( port(
clk : in std_logic; -- Clock input for timing clk : in std_logic; -- Clock input for timing
reset : in std_logic;
en_pc : in one_bit; -- activates PC en_pc : in one_bit; -- activates PC
addr_calc : in ram_addr_t; -- Address from ALU addr_calc : in ram_addr_t; -- Address from ALU
doJump : in one_bit; -- Jump to Address doJump : in one_bit; -- Jump to Address
@ -66,6 +67,7 @@ architecture implementation of cpu is
component registers component registers
port( port(
clk : in std_logic; -- input for clock (control device) clk : in std_logic; -- input for clock (control device)
reset : in std_logic;
en_reg_wb : in one_bit; -- enable register write back (?) en_reg_wb : in one_bit; -- enable register write back (?)
data_in : in word; -- Data to be written into the register data_in : in word; -- Data to be written into the register
wr_idx : in reg_idx; -- register to write to wr_idx : in reg_idx; -- register to write to
@ -133,8 +135,8 @@ architecture implementation of cpu is
signal X_addr_calc : ram_addr_t; signal X_addr_calc : ram_addr_t;
-- Clock signals -- Clock signals
signal reset : std_logic; signal reset : std_logic := '0';
signal locked : std_logic; signal locked : std_logic := '0';
------------------------- -------------------------
-- additional ALU signals -- additional ALU signals
@ -151,6 +153,7 @@ begin
-- External assignments -- External assignments
s_clock <= clk; s_clock <= clk;
reset <= rst;
ram_enable_writing <= s_ram_enable; ram_enable_writing <= s_ram_enable;
instruction_pointer <= s_instAddr; instruction_pointer <= s_instAddr;
data_address <= s_data_in_addr; data_address <= s_data_in_addr;
@ -170,6 +173,7 @@ begin
registers_RISCV : registers registers_RISCV : registers
port map( port map(
clk => s_clock, clk => s_clock,
reset => reset,
en_reg_wb => s_reg_wb_enable, en_reg_wb => s_reg_wb_enable,
data_in => reg_data_in, data_in => reg_data_in,
wr_idx => s_idx_wr, wr_idx => s_idx_wr,
@ -190,6 +194,7 @@ begin
pc_RISCV : pc pc_RISCV : pc
port map( port map(
clk => s_clock, clk => s_clock,
reset => reset,
en_pc => s_pc_enable, en_pc => s_pc_enable,
addr_calc => X_addr_calc, addr_calc => X_addr_calc,
doJump => s_pc_jump_enable, doJump => s_pc_jump_enable,
@ -243,7 +248,6 @@ begin
when others => aluIn1 <= s_reg_data1; when others => aluIn1 <= s_reg_data1;
end case; end case;
-- TODO: why line from pc to alu inp1?
-- connect input 2 -- connect input 2
case s_opcode is case s_opcode is
when uADDI | uSLTI | uSLTIU | uXORI | uORI | uANDI => aluIn2 <= s_immediate; when uADDI | uSLTI | uSLTIU | uXORI | uORI | uANDI => aluIn2 <= s_immediate;
@ -313,7 +317,7 @@ begin
end process; end process;
-- pc cycle control -- pc cycle control
pc_cycle_control : process(s_clock) pc_cycle_control : process(s_clock, reset)
begin begin
if rising_edge(s_clock) then if rising_edge(s_clock) then
case s_cycle_cnt is case s_cycle_cnt is
@ -323,6 +327,10 @@ begin
when stEXEC => s_cycle_cnt <= stWB; when stEXEC => s_cycle_cnt <= stWB;
when others => s_cycle_cnt <= stIF; when others => s_cycle_cnt <= stIF;
end case; end case;
else
if falling_edge(reset) then
s_cycle_cnt <= stIF;
end if;
end if; end if;
end process pc_cycle_control; end process pc_cycle_control;

27
src/pc.vhd
View File

@ -12,35 +12,44 @@ use work.riscv_types.all;
-- Entity PC: entity defining the pins and ports of the programmcounter -- Entity PC: entity defining the pins and ports of the programmcounter
entity pc is entity pc is
port (clk : in std_logic; -- Clock input for timing port (clk : in std_logic; -- Clock input for timing
reset : in std_logic;
en_pc : in one_bit; -- activates PC en_pc : in one_bit; -- activates PC
addr_calc : in ram_addr_t; -- Address from ALU addr_calc : in ram_addr_t; -- Address from ALU
doJump : in one_bit; -- Jump to Address doJump : in one_bit; -- Jump to Address
addr : out ram_addr_t -- Address to Decoder addr : out ram_addr_t -- Address to Decoder
); );
end PC; end PC;
architecture pro_count of pc is architecture pro_count of pc is
signal addr_out : ram_addr_t := (others => '0'); signal addr_out : ram_addr_t := (others => '0');
signal addr_out_plus : ram_addr_t := (others => '0'); signal addr_out_plus : ram_addr_t := (others => '0');
begin begin
process (clk) process (clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
if en_pc = "1" then if en_pc = "1" then
-- count -- count
if doJump = "1" then if doJump = "1" then
addr_out <= addr_calc; addr_out <= addr_calc;
-- jump -- jump
else else
addr_out <= addr_out_plus; addr_out <= addr_out_plus;
end if; end if;
end if; end if;
end if; end if;
end process; end process;
process (reset)
begin
if falling_edge(reset) then
addr_out <= (others => '0');
addr_out_plus <= (others => '0');
end if;
end process;
addr_out_plus <= (std_logic_vector(to_unsigned(to_integer(unsigned(addr_out)) + 4, ram_addr_size))); addr_out_plus <= (std_logic_vector(to_unsigned(to_integer(unsigned(addr_out)) + 4, ram_addr_size)));
addr <= addr_out; addr <= addr_out;
end pro_count; end pro_count;

14
src/registers.vhd
View File

@ -22,6 +22,7 @@ entity registers is
generic (initRegs : regFile := (others => (others => '0'))); generic (initRegs : regFile := (others => (others => '0')));
port( port(
clk : in std_logic; -- input for clock (control device) clk : in std_logic; -- input for clock (control device)
reset : in std_logic;
en_reg_wb : in one_bit; -- enable register write back (?) en_reg_wb : in one_bit; -- enable register write back (?)
data_in : in word; -- Data to be written into the register data_in : in word; -- Data to be written into the register
wr_idx : in reg_idx; -- register to write to wr_idx : in reg_idx; -- register to write to
@ -50,8 +51,17 @@ begin
registerbench(0) <= std_logic_vector(to_unsigned(0, wordWidth)); registerbench(0) <= std_logic_vector(to_unsigned(0, wordWidth));
end if; end if;
end process; end process;
-- reset if reset is activated
process (reset)
begin
if falling_edge(reset) then
registerbench <= initRegs;
end if;
end process;
-- read from both reading registers -- read from both reading registers
r1_out <= registerbench(to_integer(unsigned(r1_idx))); r1_out <= registerbench(to_integer(unsigned(r1_idx)));
r2_out <= registerbench(to_integer(unsigned(r2_idx))); r2_out <= registerbench(to_integer(unsigned(r2_idx)));
end structure; end structure;

9
tb/tb_cpu.vhd
View File

@ -13,11 +13,9 @@ end cpu_tb;
architecture Behavioral of cpu_tb is architecture Behavioral of cpu_tb is
-- Clock -- Clock and Reset
signal clk : std_logic; signal clk : std_logic;
-- Inputs
-- Outputs -- Outputs
-- Clock period definitions -- Clock period definitions
constant clk_period : time := 10 ns; constant clk_period : time := 10 ns;
@ -76,6 +74,11 @@ begin
write(lineBuffer, string'("Start the simulator")); write(lineBuffer, string'("Start the simulator"));
writeline(output, lineBuffer); writeline(output, lineBuffer);
wait for 100 ns;
cpu_reset <= '1';
wait for 17 ns;
cpu_reset <= '0';
wait; wait;
end process; end process;
end architecture; end architecture;

207
tb/tb_pc.vhd
View File

@ -18,116 +18,119 @@ end pc_tb;
-- Architecture testing of pc_tb: testing calculations -- Architecture testing of pc_tb: testing calculations
architecture testing of pc_tb is architecture testing of pc_tb is
-- clock definition -- clock definition
signal clk : std_logic; signal clk : std_logic;
constant clk_period : time := 10 ns; constant clk_period : time := 10 ns;
-- Inputs pc
signal en_pc : one_bit;
signal addr_calc : ram_addr_t;
signal doJump : one_bit;
-- Outputs pc
signal addr : ram_addr_t;
-- unittest signals pc
signal addr_calc_tb : ram_addr_t;
signal reset : std_logic;
-- Inputs pc
signal en_pc : one_bit;
signal addr_calc : ram_addr_t;
signal doJump : one_bit;
-- Outputs pc
signal addr : ram_addr_t;
-- unittest signals pc
signal addr_calc_tb : ram_addr_t;
begin begin
-- Entity work.pc(pro_count): Init of Unit Under Test -- Entity work.pc(pro_count): Init of Unit Under Test
uut1 : entity work.pc uut1 : entity work.pc
port map ( port map (
clk => clk, clk => clk,
en_pc => en_pc, reset => reset,
addr_calc => addr_calc, en_pc => en_pc,
doJump => doJump, addr_calc => addr_calc,
addr => addr doJump => doJump,
); addr => addr
);
-- Process clk_process operating the clock
clk_process : process -- runs only, when changed
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Process stim_proc control device for uut -- Process clk_process operating the clock
stim_proc : process -- runs only, when changed clk_process : process -- runs only, when changed
-- Text I/O begin
variable lineBuffer : line; clk <= '0';
begin wait for clk_period/2;
clk <= '1';
-- wait for the rising edge wait for clk_period/2;
wait until rising_edge(clk); end process;
wait for 10 ns;
-- Print the top element
write(lineBuffer, string'("Start the simulator"));
writeline(output, lineBuffer);
-- testcases -- Process stim_proc control device for uut
stim_proc : process -- runs only, when changed
-- Case 1: addr_calc -- Text I/O
write(lineBuffer, string'("Testing Case 1: ")); variable lineBuffer : line;
writeline(output, lineBuffer); begin
en_pc <= std_logic_vector(to_unsigned(1, 1)); -- wait for the rising edge
doJump <= std_logic_vector(to_unsigned(1, 1)); wait until rising_edge(clk);
addr_calc <= std_logic_vector(to_unsigned(30, ram_addr_size));
wait for 10 ns;
if addr = std_logic_vector(to_unsigned(30, ram_addr_size)) then wait for 10 ns;
write(lineBuffer, string'("Result 1: +"));
writeline(output, lineBuffer);
else
write(lineBuffer, string'("Result 1: -"));
writeline(output, lineBuffer);
end if;
-- Case 2: count
write(lineBuffer, string'("Testing Case 2: "));
writeline(output, lineBuffer);
en_pc <= std_logic_vector(to_unsigned(1, 1)); -- Print the top element
doJump <= std_logic_vector(to_unsigned(0, 1)); write(lineBuffer, string'("Start the simulator"));
addr_calc <= std_logic_vector(to_unsigned(60, ram_addr_size)); writeline(output, lineBuffer);
wait for 10 ns;
--same value from
if addr = std_logic_vector(to_unsigned(31, ram_addr_size)) then
write(lineBuffer, string'("Result 2: +"));
writeline(output, lineBuffer);
else
write(lineBuffer, string'("Result 2: -"));
writeline(output, lineBuffer);
end if;
-- Case 3: hold -- testcases
write(lineBuffer, string'("Testing Case 3: "));
writeline(output, lineBuffer);
en_pc <= std_logic_vector(to_unsigned(0, 1)); -- Case 1: addr_calc
doJump <= std_logic_vector(to_unsigned(0, 1)); write(lineBuffer, string'("Testing Case 1: "));
addr_calc <= std_logic_vector(to_unsigned(90, ram_addr_size)); writeline(output, lineBuffer);
wait for 10 ns;
--same value from
if addr = std_logic_vector(to_unsigned(31, ram_addr_size)) then
write(lineBuffer, string'("Result 3: +"));
writeline(output, lineBuffer);
else
write(lineBuffer, string'("Result 3: -"));
writeline(output, lineBuffer);
end if;
-- I'm still waiting en_pc <= std_logic_vector(to_unsigned(1, 1));
wait; doJump <= std_logic_vector(to_unsigned(1, 1));
end process; addr_calc <= std_logic_vector(to_unsigned(30, ram_addr_size));
wait for 10 ns;
if addr = std_logic_vector(to_unsigned(30, ram_addr_size)) then
write(lineBuffer, string'("Result 1: +"));
writeline(output, lineBuffer);
else
write(lineBuffer, string'("Result 1: -"));
writeline(output, lineBuffer);
end if;
-- Case 2: count
write(lineBuffer, string'("Testing Case 2: "));
writeline(output, lineBuffer);
en_pc <= std_logic_vector(to_unsigned(1, 1));
doJump <= std_logic_vector(to_unsigned(0, 1));
addr_calc <= std_logic_vector(to_unsigned(60, ram_addr_size));
wait for 10 ns;
--same value from
if addr = std_logic_vector(to_unsigned(31, ram_addr_size)) then
write(lineBuffer, string'("Result 2: +"));
writeline(output, lineBuffer);
else
write(lineBuffer, string'("Result 2: -"));
writeline(output, lineBuffer);
end if;
-- Case 3: hold
write(lineBuffer, string'("Testing Case 3: "));
writeline(output, lineBuffer);
en_pc <= std_logic_vector(to_unsigned(0, 1));
doJump <= std_logic_vector(to_unsigned(0, 1));
addr_calc <= std_logic_vector(to_unsigned(90, ram_addr_size));
wait for 10 ns;
--same value from
if addr = std_logic_vector(to_unsigned(31, ram_addr_size)) then
write(lineBuffer, string'("Result 3: +"));
writeline(output, lineBuffer);
else
write(lineBuffer, string'("Result 3: -"));
writeline(output, lineBuffer);
end if;
-- I'm still waiting
wait;
end process;
end testing; end testing;

377
tb/tb_reg.vhd
View File

@ -12,7 +12,7 @@ library work;
use work.riscv_types.all; use work.riscv_types.all;
library std; library std;
use std.textio.all; use std.textio.all;
-- Entity regs_tb: Entity providing testinputs, receiving testoutputs for registerbench -- Entity regs_tb: Entity providing testinputs, receiving testoutputs for registerbench
entity regs_tb is entity regs_tb is
@ -20,212 +20,215 @@ end regs_tb;
-- Architecture testing of regs_tb: testing read / write operations -- Architecture testing of regs_tb: testing read / write operations
architecture testing of regs_tb is architecture testing of regs_tb is
-- clock definition -- clock definition
signal clk : std_logic; signal clk : std_logic;
constant clk_period : time := 10 ns; constant clk_period : time := 10 ns;
-- Inputs -- Inputs
signal en_reg_wb_tb : one_bit; signal en_reg_wb_tb : one_bit;
signal data_in_tb : word; signal data_in_tb : word;
signal wr_idx_tb : reg_idx; signal wr_idx_tb : reg_idx;
signal r1_idx_tb : reg_idx; signal r1_idx_tb : reg_idx;
signal r2_idx_tb : reg_idx; signal r2_idx_tb : reg_idx;
signal write_enable_tb : one_bit; signal write_enable_tb : one_bit;
-- Outputs -- Outputs
signal r1_out_tb : word; signal r1_out_tb : word;
signal r2_out_tb : word; signal r2_out_tb : word;
-- unittest signals -- unittest signals
signal random_slv: word; signal random_slv : word;
--function for random_std_logic_vector
function get_random_slv return std_logic_vector is
-- random number variablen
variable seed1 : integer := 1;
variable seed2 : integer := 1;
variable r : real;
variable slv : std_logic_vector(wordWidth - 1 downto 0);
begin signal reset : std_logic;
for i in slv'range loop
uniform(seed1, seed2, r); --function for random_std_logic_vector
slv(i) := '1' when r > 0.5 else '0'; function get_random_slv return std_logic_vector is
end loop;
return slv; -- random number variablen
end function; variable seed1 : integer := 1;
variable seed2 : integer := 1;
variable r : real;
variable slv : std_logic_vector(wordWidth - 1 downto 0);
begin
for i in slv'range loop
uniform(seed1, seed2, r);
slv(i) := '1' when r > 0.5 else '0';
end loop;
return slv;
end function;
begin begin
-- Init of Unit Under Test
uut : entity work.registers(Structure)
port map (
clk => clk,
en_reg_wb => en_reg_wb_tb,
data_in => data_in_tb,
wr_idx => wr_idx_tb,
r1_idx => r1_idx_tb,
r2_idx => r2_idx_tb,
write_enable => write_enable_tb,
r1_out => r1_out_tb,
r2_out => r2_out_tb
);
-- Process clk_process operating the clock -- Init of Unit Under Test
clk_process : process -- runs always uut : entity work.registers(Structure)
begin port map (
clk <= '0'; clk => clk,
wait for clk_period/2; reset => reset,
clk <= '1'; en_reg_wb => en_reg_wb_tb,
wait for clk_period/2; data_in => data_in_tb,
end process; wr_idx => wr_idx_tb,
r1_idx => r1_idx_tb,
-- Stimulating the UUT r2_idx => r2_idx_tb,
-- Process stim_proc control device for write_enable => write_enable_tb,
stim_proc : process r1_out => r1_out_tb,
-- Text I/O r2_out => r2_out_tb
variable lineBuffer : line; );
begin
-- wait for the rising edge
wait until rising_edge(clk);
wait for 5 ns;
-- Print the top element
write(lineBuffer, string'("Start the simulation: "));
writeline(output, lineBuffer);
-- set the stimuli here -- Process clk_process operating the clock
clk_process : process -- runs always
-- Case 1: write to x=7 + read x=4 begin
write(lineBuffer, string'("Testing Case 1: ")); clk <= '0';
writeline(output, lineBuffer); wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
write_enable_tb <= std_logic_vector(to_unsigned(1, 1)); -- Stimulating the UUT
data_in_tb<= std_logic_vector(to_unsigned(7, wordWidth)); -- Process stim_proc control device for
wr_idx_tb <= std_logic_vector(to_unsigned(7, reg_adr_size)); stim_proc : process
r1_idx_tb <= std_logic_vector(to_unsigned(4, reg_adr_size)); -- Text I/O
r2_idx_tb <= std_logic_vector(to_unsigned(7, reg_adr_size)); variable lineBuffer : line;
wait for 10 ns;
if r1_out_tb = std_logic_vector(to_unsigned(0, wordWidth)) and r2_out_tb = std_logic_vector(to_unsigned(7, wordWidth)) then begin
write(lineBuffer, string'("Result 1: +"));
writeline(output, lineBuffer);
else
write(lineBuffer, string'("Result 1: -"));
writeline(output, lineBuffer);
end if;
-- Case 2: write to x=27 + read x=0 -- wait for the rising edge
write(lineBuffer, string'("Testing Case 2: ")); wait until rising_edge(clk);
writeline(output, lineBuffer);
write_enable_tb <= std_logic_vector(to_unsigned(1, 1)); wait for 5 ns;
data_in_tb<= std_logic_vector(to_unsigned(7, wordWidth));
wr_idx_tb <= std_logic_vector(to_unsigned(27, reg_adr_size));
r1_idx_tb <= std_logic_vector(to_unsigned(0, reg_adr_size));
r2_idx_tb <= std_logic_vector(to_unsigned(27, reg_adr_size));
wait for 10 ns;
if r1_out_tb = std_logic_vector(to_unsigned(0, wordWidth)) and r2_out_tb = std_logic_vector(to_unsigned(7, wordWidth)) then -- Print the top element
write(lineBuffer, string'("Result 2: +")); write(lineBuffer, string'("Start the simulation: "));
writeline(output, lineBuffer); writeline(output, lineBuffer);
else
write(lineBuffer, string'("Result 2: -"));
writeline(output, lineBuffer);
end if;
-- Case 3: write to zero + read from zero x2 -- set the stimuli here
write(lineBuffer, string'("Testing Case 3: "));
writeline(output, lineBuffer);
write_enable_tb <= std_logic_vector(to_unsigned(1, 1)); -- Case 1: write to x=7 + read x=4
data_in_tb<= std_logic_vector(to_unsigned(7, wordWidth)); write(lineBuffer, string'("Testing Case 1: "));
wr_idx_tb <= std_logic_vector(to_unsigned(0, reg_adr_size)); writeline(output, lineBuffer);
r1_idx_tb <= std_logic_vector(to_unsigned(0, reg_adr_size));
r2_idx_tb <= std_logic_vector(to_unsigned(27, reg_adr_size));
wait for 10 ns;
if r1_out_tb = std_logic_vector(to_unsigned(0, wordWidth)) then write_enable_tb <= std_logic_vector(to_unsigned(1, 1));
write(lineBuffer, string'("Result 3: +")); data_in_tb <= std_logic_vector(to_unsigned(7, wordWidth));
writeline(output, lineBuffer); wr_idx_tb <= std_logic_vector(to_unsigned(7, reg_adr_size));
else r1_idx_tb <= std_logic_vector(to_unsigned(4, reg_adr_size));
write(lineBuffer, string'("Result 3: -")); r2_idx_tb <= std_logic_vector(to_unsigned(7, reg_adr_size));
writeline(output, lineBuffer); wait for 10 ns;
end if;
-- Case 4: write to 31 + read from 31 if r1_out_tb = std_logic_vector(to_unsigned(0, wordWidth)) and r2_out_tb = std_logic_vector(to_unsigned(7, wordWidth)) then
write(lineBuffer, string'("Testing Case 4: ")); write(lineBuffer, string'("Result 1: +"));
writeline(output, lineBuffer); writeline(output, lineBuffer);
else
write(lineBuffer, string'("Result 1: -"));
writeline(output, lineBuffer);
end if;
write_enable_tb <= std_logic_vector(to_unsigned(1, 1)); -- Case 2: write to x=27 + read x=0
data_in_tb<= std_logic_vector(to_unsigned(7, wordWidth)); write(lineBuffer, string'("Testing Case 2: "));
wr_idx_tb <= std_logic_vector(to_unsigned(31, reg_adr_size)); writeline(output, lineBuffer);
r1_idx_tb <= std_logic_vector(to_unsigned(31, reg_adr_size));
r2_idx_tb <= std_logic_vector(to_unsigned(0, reg_adr_size));
wait for 10 ns;
if r1_out_tb = std_logic_vector(to_unsigned(7, wordWidth)) then write_enable_tb <= std_logic_vector(to_unsigned(1, 1));
write(lineBuffer, string'("Result 4: +")); data_in_tb <= std_logic_vector(to_unsigned(7, wordWidth));
writeline(output, lineBuffer); wr_idx_tb <= std_logic_vector(to_unsigned(27, reg_adr_size));
else r1_idx_tb <= std_logic_vector(to_unsigned(0, reg_adr_size));
write(lineBuffer, string'("Result 4: -")); r2_idx_tb <= std_logic_vector(to_unsigned(27, reg_adr_size));
writeline(output, lineBuffer); wait for 10 ns;
end if;
-- Case 5: read x=7 + read x=18 if r1_out_tb = std_logic_vector(to_unsigned(0, wordWidth)) and r2_out_tb = std_logic_vector(to_unsigned(7, wordWidth)) then
write(lineBuffer, string'("Testing Case 5: ")); write(lineBuffer, string'("Result 2: +"));
writeline(output, lineBuffer); writeline(output, lineBuffer);
else
write(lineBuffer, string'("Result 2: -"));
writeline(output, lineBuffer);
end if;
write_enable_tb <= std_logic_vector(to_unsigned(0, 1)); -- Case 3: write to zero + read from zero x2
data_in_tb<= std_logic_vector(to_unsigned(9, wordWidth)); write(lineBuffer, string'("Testing Case 3: "));
wr_idx_tb <= std_logic_vector(to_unsigned(7, reg_adr_size)); writeline(output, lineBuffer);
r1_idx_tb <= std_logic_vector(to_unsigned(7, reg_adr_size));
r2_idx_tb <= std_logic_vector(to_unsigned(18, reg_adr_size)); write_enable_tb <= std_logic_vector(to_unsigned(1, 1));
wait for 10 ns; data_in_tb <= std_logic_vector(to_unsigned(7, wordWidth));
wr_idx_tb <= std_logic_vector(to_unsigned(0, reg_adr_size));
-- Not allowed to change, last value was 7, new "would" be 9 r1_idx_tb <= std_logic_vector(to_unsigned(0, reg_adr_size));
if r1_out_tb = std_logic_vector(to_unsigned(7, wordWidth)) then r2_idx_tb <= std_logic_vector(to_unsigned(27, reg_adr_size));
write(lineBuffer, string'("Result 5: +")); wait for 10 ns;
writeline(output, lineBuffer);
else if r1_out_tb = std_logic_vector(to_unsigned(0, wordWidth)) then
write(lineBuffer, string'("Result 5: -")); write(lineBuffer, string'("Result 3: +"));
writeline(output, lineBuffer); writeline(output, lineBuffer);
end if; else
write(lineBuffer, string'("Result 3: -"));
-- Case 6: RANDOM_Test write to 12 + read from 12 writeline(output, lineBuffer);
write(lineBuffer, string'("Testing Case 6: ")); end if;
writeline(output, lineBuffer);
-- Case 4: write to 31 + read from 31
-- get random_logic_vector write(lineBuffer, string'("Testing Case 4: "));
random_slv <= get_random_slv; writeline(output, lineBuffer);
wait for 10 ns; write_enable_tb <= std_logic_vector(to_unsigned(1, 1));
data_in_tb <= std_logic_vector(to_unsigned(7, wordWidth));
write_enable_tb <= std_logic_vector(to_unsigned(1, 1)); wr_idx_tb <= std_logic_vector(to_unsigned(31, reg_adr_size));
data_in_tb <= random_slv; r1_idx_tb <= std_logic_vector(to_unsigned(31, reg_adr_size));
wr_idx_tb <= std_logic_vector(to_unsigned(12, reg_adr_size)); r2_idx_tb <= std_logic_vector(to_unsigned(0, reg_adr_size));
r1_idx_tb <= std_logic_vector(to_unsigned(12, reg_adr_size)); wait for 10 ns;
r2_idx_tb <= std_logic_vector(to_unsigned(0, reg_adr_size));
wait for 10 ns; if r1_out_tb = std_logic_vector(to_unsigned(7, wordWidth)) then
write(lineBuffer, string'("Result 4: +"));
if r1_out_tb = random_slv then writeline(output, lineBuffer);
write(lineBuffer, string'("Result 6: +")); else
writeline(output, lineBuffer); write(lineBuffer, string'("Result 4: -"));
else writeline(output, lineBuffer);
write(lineBuffer, string'("Result 6: -")); end if;
writeline(output, lineBuffer);
end if; -- Case 5: read x=7 + read x=18
write(lineBuffer, string'("Testing Case 5: "));
-- end simulation writeline(output, lineBuffer);
write(lineBuffer, string'("end of simulation"));
writeline(output, lineBuffer); write_enable_tb <= std_logic_vector(to_unsigned(0, 1));
data_in_tb <= std_logic_vector(to_unsigned(9, wordWidth));
wr_idx_tb <= std_logic_vector(to_unsigned(7, reg_adr_size));
r1_idx_tb <= std_logic_vector(to_unsigned(7, reg_adr_size));
r2_idx_tb <= std_logic_vector(to_unsigned(18, reg_adr_size));
wait for 10 ns;
-- Not allowed to change, last value was 7, new "would" be 9
if r1_out_tb = std_logic_vector(to_unsigned(7, wordWidth)) then
write(lineBuffer, string'("Result 5: +"));
writeline(output, lineBuffer);
else
write(lineBuffer, string'("Result 5: -"));
writeline(output, lineBuffer);
end if;
-- Case 6: RANDOM_Test write to 12 + read from 12
write(lineBuffer, string'("Testing Case 6: "));
writeline(output, lineBuffer);
-- get random_logic_vector
random_slv <= get_random_slv;
wait for 10 ns;
write_enable_tb <= std_logic_vector(to_unsigned(1, 1));
data_in_tb <= random_slv;
wr_idx_tb <= std_logic_vector(to_unsigned(12, reg_adr_size));
r1_idx_tb <= std_logic_vector(to_unsigned(12, reg_adr_size));
r2_idx_tb <= std_logic_vector(to_unsigned(0, reg_adr_size));
wait for 10 ns;
if r1_out_tb = random_slv then
write(lineBuffer, string'("Result 6: +"));
writeline(output, lineBuffer);
else
write(lineBuffer, string'("Result 6: -"));
writeline(output, lineBuffer);
end if;
-- end simulation
write(lineBuffer, string'("end of simulation"));
writeline(output, lineBuffer);
-- I'm still waiting
wait;
end process;
-- I'm still waiting
wait;
end process;
end testing; end testing;