.gitignore

@@ -3,4 +3,3 @@
 *.cf
 xvhdl*
 Vivado*
-*_tb

src/cpu.vhd

@@ -29,7 +29,6 @@ architecture implementation of cpu is
   component pc
     port(
       clk       : in  std_logic;        -- Clock input for timing
-      reset     : in  std_logic;
       en_pc     : in  one_bit;          -- activates PC
       addr_calc : in  ram_addr_t;       -- Address from ALU
       doJump    : in  one_bit;          -- Jump to Address
@@ -67,7 +66,6 @@ architecture implementation of cpu is
   component registers
     port(
       clk          : in  std_logic;     -- input for clock (control device)
-      reset        : in  std_logic;
       en_reg_wb    : in  one_bit;       -- enable register write back (?)
       data_in      : in  word;          -- Data to be written into the register
       wr_idx       : in  reg_idx;       -- register to write to
@@ -135,8 +133,8 @@ architecture implementation of cpu is
   signal X_addr_calc : ram_addr_t;
 
   -- Clock signals
-  signal reset  : std_logic := '0';
-  signal locked : std_logic := '0';
+  signal reset  : std_logic;
+  signal locked : std_logic;
 
 -------------------------
 -- additional ALU signals
@@ -153,7 +151,6 @@ begin
 
   -- External assignments
   s_clock             <= clk;
-  reset               <= rst;
   ram_enable_writing  <= s_ram_enable;
   instruction_pointer <= s_instAddr;
   data_address        <= s_data_in_addr;
@@ -173,7 +170,6 @@ begin
   registers_RISCV : registers
     port map(
       clk          => s_clock,
-      reset        => reset,
       en_reg_wb    => s_reg_wb_enable,
       data_in      => reg_data_in,
       wr_idx       => s_idx_wr,
@@ -194,7 +190,6 @@ begin
   pc_RISCV : pc
     port map(
       clk       => s_clock,
-      reset     => reset,
       en_pc     => s_pc_enable,
       addr_calc => X_addr_calc,
       doJump    => s_pc_jump_enable,
@@ -248,6 +243,7 @@ begin
       when others => aluIn1 <= s_reg_data1;
     end case;
 
+    -- TODO: why line from pc to alu inp1?
     -- connect input 2
     case s_opcode is
       when uADDI | uSLTI | uSLTIU | uXORI | uORI | uANDI => aluIn2 <= s_immediate;
@@ -317,7 +313,7 @@ begin
   end process;
 
   -- pc cycle control
-  pc_cycle_control : process(s_clock, reset)
+  pc_cycle_control : process(s_clock)
   begin
     if rising_edge(s_clock) then
       case s_cycle_cnt is
@@ -327,10 +323,6 @@ begin
         when stEXEC => s_cycle_cnt <= stWB;
         when others => s_cycle_cnt <= stIF;
       end case;
-    else
-      if falling_edge(reset) then
-        s_cycle_cnt <= stIF;
-      end if;
     end if;
   end process pc_cycle_control;
 

src/pc.vhd

@@ -12,7 +12,6 @@ use work.riscv_types.all;
 -- Entity PC: entity defining the pins and ports of the programmcounter
 entity pc is
   port (clk       : in  std_logic;      -- Clock input for timing
-        reset     : in  std_logic;
         en_pc     : in  one_bit;        -- activates PC
         addr_calc : in  ram_addr_t;     -- Address from ALU
         doJump    : in  one_bit;        -- Jump to Address
@@ -41,14 +40,6 @@ begin
     end if;
   end process;
   
-  process (reset)
-  begin
-    if falling_edge(reset) then
-      addr_out      <= (others => '0');
-      addr_out_plus <= (others => '0');
-    end if;
-  end process;
-
   addr_out_plus <= (std_logic_vector(to_unsigned(to_integer(unsigned(addr_out)) + 4, ram_addr_size)));
   addr <= addr_out;
   

src/registers.vhd

@@ -22,7 +22,6 @@ entity registers is
     generic (initRegs : regFile := (others => (others => '0')));
     port(
         clk          : in  std_logic;   -- input for clock (control device)
-        reset        : in  std_logic;
         en_reg_wb    : in  one_bit;     -- enable register write back (?)
         data_in      : in  word;        -- Data to be written into the register
         wr_idx       : in  reg_idx;     -- register to write to
@@ -51,15 +50,6 @@ begin
             registerbench(0) <= std_logic_vector(to_unsigned(0, wordWidth));
         end if;
     end process;
-
-    -- reset if reset is activated
-    process (reset)
-    begin
-        if falling_edge(reset) then
-            registerbench <= initRegs;
-        end if;
-    end process;
-
     -- read from both reading registers
     r1_out  <= registerbench(to_integer(unsigned(r1_idx)));
     r2_out  <= registerbench(to_integer(unsigned(r2_idx)));

tb/tb_cpu.vhd

@@ -13,9 +13,11 @@ end cpu_tb;
 
 architecture Behavioral of cpu_tb is
 
-  -- Clock and Reset
+  -- Clock
   signal clk : std_logic;
 
+  -- Inputs
+
   -- Outputs
   -- Clock period definitions
   constant clk_period : time := 10 ns;
@@ -74,11 +76,6 @@ begin
     write(lineBuffer, string'("Start the simulator"));
     writeline(output, lineBuffer);
 
-    wait for 100 ns;
-    cpu_reset <= '1';
-    wait for 17 ns;
-    cpu_reset <= '0';
-
     wait;
   end process;
 end architecture;

tb/tb_pc.vhd

@@ -33,14 +33,11 @@ architecture testing of pc_tb is
 	-- unittest signals pc
 	signal addr_calc_tb	: ram_addr_t;
 	
-    signal reset : std_logic;
-
 begin
 	-- Entity work.pc(pro_count): Init of Unit Under Test
 	uut1 : entity work.pc
 		port map (			
 			clk		=> clk,
-            reset     => reset,
 			en_pc		=> en_pc,
 			addr_calc 	=> addr_calc,
 			doJump		=> doJump,

tb/tb_reg.vhd

@@ -39,8 +39,6 @@ architecture testing of regs_tb is
 	-- unittest signals
 	signal random_slv: word;
 	
-    signal reset : std_logic;
-
 	--function for random_std_logic_vector
 	function get_random_slv return std_logic_vector is
 	
@@ -64,7 +62,6 @@ begin
 	uut : entity work.registers(Structure)
 		port map (
 			clk => clk,
-            reset        => reset,
 			en_reg_wb => en_reg_wb_tb,
 			data_in => data_in_tb,
 			wr_idx => wr_idx_tb,