70 lines
1.8 KiB
VHDL
70 lines
1.8 KiB
VHDL
-- branch.vhd
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-- Created on: 19:01:2023
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-- Author(s): Yannick Reiß
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-- Copyright: WTFPL
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-- Content: Entity branch - enable B-types in CPU
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library work;
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use work.riscv_types.all;
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entity Branch is
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port (
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op_code : in uOP;
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reg1 : in word;
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reg2 : in word;
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jmp_enable : out one_bit
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);
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end Branch;
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architecture arch of Branch is
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begin
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branch_process : process(op_code)
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begin
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case op_code is
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when uBEQ =>
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if reg1 = reg2 then
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jmp_enable <= "1";
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else
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jmp_enable <= "0";
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end if;
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when uBNE =>
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if not (reg1 = reg2) then
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jmp_enable <= "1";
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else
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jmp_enable <= "0";
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end if;
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when uBLT =>
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if signed(reg1) < signed(reg2) then
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jmp_enable <= "1";
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else
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jmp_enable <= "0";
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end if;
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when uBGE =>
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if signed(reg1) >= signed(reg2) then
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jmp_enable <= "1";
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else
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jmp_enable <= "0";
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end if;
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when uBLTU =>
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if unsigned(reg1) < unsigned(reg2) then
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jmp_enable <= "1";
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else
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jmp_enable <= "0";
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end if;
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when uBGEU =>
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if unsigned(reg1) >= unsigned(reg2) then
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jmp_enable <= "1";
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else
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jmp_enable <= "0";
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end if;
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when others =>
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jmp_enable <= "0";
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end case;
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end process; -- branch
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end architecture; -- arch
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