50 lines
919 B
VHDL
50 lines
919 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.riscv_types.all;
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library std;
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use std.textio.all;
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entity cpu_tb is
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end cpu_tb;
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architecture Behavioral of cpu_tb is
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-- Clock
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signal clk : std_logic;
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-- Inputs
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-- Outputs
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-- Clock period definitions
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constant clk_period : time := 10 ns;
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begin
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-- Instantiate the Unit Under Test (UUT)
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uut : entity work.cpu(implementation)
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port map (clk => clk);
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-- Clock process definitions
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clk_process : process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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-- Process stim_proc stimulate uut
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stim_proc : process -- runs only, when changed
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variable lineBuffer : line;
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begin
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write(lineBuffer, string'("Start the simulator"));
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writeline(output, lineBuffer);
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wait for 0 ns;
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end process;
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end architecture;
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