78 lines
1.6 KiB
VHDL
78 lines
1.6 KiB
VHDL
-- tb_imm.vhd
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-- Created on: Tu 10. Jan 21:10:00 CET 2023
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-- Author(s): Yannick Reiß
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-- Content: testbench for immediate entity
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library work;
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use work.riscv_types.all;
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library std;
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use std.textio.all;
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-- Entity imm_tb: dummy entity
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entity imm_tb is
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end imm_tb;
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architecture testing of imm_tb is
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-- clock definition
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signal clk : std_logic;
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constant clk_period : time := 10 ns;
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-- inputs imm
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signal s_instruction : instruction;
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signal s_opcode : uOP;
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-- outputs imm
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signal s_immediate : word;
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begin
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uut : entity work.imm
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port map(
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instruction => s_instruction,
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opcode => s_opcode,
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immediate => s_immediate
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);
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-- Process clk_process operating the clock
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clk_process : process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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-- stimulation process
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stim_proc : process
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variable lineBuffer : line;
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begin
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-- wait for the rising edge
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wait until rising_edge(clk);
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wait for 10 ns;
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write(lineBuffer, string'("Start the simulator"));
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writeline(output, lineBuffer);
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-- testcases
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-- addi x3, x0, 5
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s_instruction <= x"00500193";
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s_opcode <= uADDI;
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wait for 10 ns;
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-- addi x2, x0, 1
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s_instruction <= x"00100113";
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s_opcode <= uADDI;
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wait;
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end process;
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end architecture; -- testing
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