107 lines
2.7 KiB
VHDL
107 lines
2.7 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.riscv_types.all;
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library std;
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use std.textio.all;
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entity ram_tb is
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end ram_tb;
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architecture Behavioral of ram_tb is
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-- Clock
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signal clk : std_logic;
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-- Inputs
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signal addr_a : std_logic_vector(ram_addr_size - 1 downto 0);
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signal write_b : std_logic_vector(1-1 downto 0);
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signal addr_b : std_logic_vector(ram_addr_size - 1 downto 0);
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signal data_write_b : std_logic_vector(wordWidth - 1 downto 0);
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-- Outputs
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signal data_read_a : std_logic_vector(wordWidth - 1 downto 0);
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signal data_read_b : std_logic_vector(wordWidth - 1 downto 0);
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-- Clock period definitions
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constant clk_period : time := 10 ns;
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-- Unittest Signale
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signal tb_addr_a : integer;
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signal tb_addr_b : integer;
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signal tb_test_v : std_logic_vector(wordWidth - 1 downto 0);
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signal tb_check_v : std_logic_vector(wordWidth - 1 downto 0);
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signal tb_validate : std_logic;
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begin
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-- Instantiate the Unit Under Test (UUT)
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uut : entity work.ram(Behavioral)
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port map (clk => clk,
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instructionAdr => addr_a,
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dataAdr => addr_b,
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writeEnable => write_b,
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dataIn => data_write_b,
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instruction => data_read_a,
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dataOut => data_read_b);
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-- Clock process definitions
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clk_process : process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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-- Stimulus process
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stim_proc : process
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variable lineBuffer : line;
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begin
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wait for 5 ns;
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-- Wait for the first rising edge
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wait until rising_edge(clk);
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-- manual test
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addr_a <= "001101001110";
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addr_b <= "011100110010";
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write_b <= "1";
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wait for 10 ns;
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-- Testing Mem
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tb_validate <= '1';
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write_b <= std_logic_vector(to_unsigned(1, 1));
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for test_case in 0 to 1000 loop
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for tb_addr in 0 to 4096 loop
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-- assign test values
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tb_test_v <= std_logic_vector(to_unsigned(tb_addr, wordWidth));
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tb_check_v <= std_logic_vector(to_unsigned(tb_addr, wordWidth));
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-- Test this value
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addr_a <= std_logic_vector(to_unsigned(tb_addr, ram_addr_size));
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addr_b <= std_logic_vector(to_unsigned(tb_addr, ram_addr_size));
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data_write_b <= tb_test_v;
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if (data_read_a = tb_check_v and data_read_b = tb_check_v) then
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tb_validate <= '0';
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write(lineBuffer, string'("Everything fine!"));
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writeline(output, lineBuffer);
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else
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tb_validate <= '1';
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end if;
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wait for 10 ns;
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end loop;
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end loop;
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-- Simply wait forever
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wait;
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end process;
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end architecture;
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