82 lines
2.3 KiB
VHDL
82 lines
2.3 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.riscv_types.all;
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library std;
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use std.textio.all;
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entity cpu_tb is
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end cpu_tb;
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architecture Behavioral of cpu_tb is
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-- Clock
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signal clk : std_logic;
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-- Inputs
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-- Outputs
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-- Clock period definitions
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constant clk_period : time := 10 ns;
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-- CPU and RAM constraints
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signal cpu_reset : std_logic := '0';
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signal cpu_instruction : word := (others => '0');
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signal cpu_data : word := (others => '0');
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signal ram_enable : std_logic := '0';
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signal instr_pointer : ram_addr_t := (others => '0');
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signal ram_address : ram_addr_t := (others => '0');
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signal ram_data : word := (others => '0');
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signal ram_cut_zeros : ram_addr_t := (others => '0');
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signal instr_pointer_zeros : ram_addr_t := (others => '0');
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begin
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ram_cut_zeros <= "00000000000000000000" & ram_address(11 downto 0);
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instr_pointer_zeros <= "00000000000000000000" & instr_pointer(11 downto 0);
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-- Instantiate the Unit Under Test (UUT)
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uut : entity work.cpu(implementation)
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port map (clk => clk,
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rst => cpu_reset,
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instruction_read => cpu_instruction,
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ram_read_data => cpu_data,
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ram_enable_writing => ram_enable,
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instruction_pointer => instr_pointer,
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data_address => ram_address,
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ram_write_data => ram_data
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);
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rut : entity work.ram (behavioral)
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port map(clk => clk,
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instructionAddr => instr_pointer_zeros,
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dataAddr => ram_cut_zeros,
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writeEnable => ram_enable,
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dataIn => ram_data,
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instruction => cpu_instruction,
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dataOut => cpu_data
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);
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-- Clock process definitions
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clk_process : process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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-- Process stim_proc stimulate uut
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stim_proc : process -- runs only, when changed
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variable lineBuffer : line;
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begin
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write(lineBuffer, string'("Start the simulator"));
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writeline(output, lineBuffer);
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wait;
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end process;
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end architecture;
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