134 lines
3.2 KiB
VHDL
134 lines
3.2 KiB
VHDL
-- tb_pc.vhd
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-- Created on: Mo 05. Dec 15:44:55 CET 2022
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-- Author(s): Carl Ries, Yannick Reiß, Alexander Graf
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-- Content: Testbench for program counter
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.riscv_types.all;
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library std;
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use std.textio.all;
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-- Entity pc_tb: dummy entity
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entity pc_tb is
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end pc_tb;
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-- Architecture testing of pc_tb: testing calculations
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architecture testing of pc_tb is
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-- clock definition
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signal clk : std_logic;
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constant clk_period : time := 10 ns;
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-- Inputs pc
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signal en_pc : one_bit;
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signal addr_calc : ram_addr_t;
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signal doJump : one_bit;
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-- Outputs pc
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signal addr : ram_addr_t;
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-- unittest signals pc
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signal addr_calc_tb : ram_addr_t;
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begin
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-- Entity work.pc(pro_count): Init of Unit Under Test
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uut1 : entity work.pc
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port map (
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clk => clk,
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en_pc => en_pc,
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addr_calc => addr_calc,
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doJump => doJump,
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addr => addr
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);
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-- Process clk_process operating the clock
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clk_process : process -- runs only, when changed
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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-- Process stim_proc control device for uut
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stim_proc : process -- runs only, when changed
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-- Text I/O
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variable lineBuffer : line;
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begin
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-- wait for the rising edge
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wait until rising_edge(clk);
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wait for 10 ns;
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-- Print the top element
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write(lineBuffer, string'("Start the simulator"));
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writeline(output, lineBuffer);
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-- testcases
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-- Case 1: addr_calc
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write(lineBuffer, string'("Testing Case 1: "));
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writeline(output, lineBuffer);
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en_pc <= std_logic_vector(to_unsigned(1, 1));
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doJump <= std_logic_vector(to_unsigned(1, 1));
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addr_calc <= std_logic_vector(to_unsigned(30, ram_addr_size));
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wait for 10 ns;
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if addr = std_logic_vector(to_unsigned(30, ram_addr_size)) then
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write(lineBuffer, string'("Result 1: +"));
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writeline(output, lineBuffer);
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else
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write(lineBuffer, string'("Result 1: -"));
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writeline(output, lineBuffer);
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end if;
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-- Case 2: count
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write(lineBuffer, string'("Testing Case 2: "));
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writeline(output, lineBuffer);
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en_pc <= std_logic_vector(to_unsigned(1, 1));
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doJump <= std_logic_vector(to_unsigned(0, 1));
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addr_calc <= std_logic_vector(to_unsigned(60, ram_addr_size));
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wait for 10 ns;
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--same value from
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if addr = std_logic_vector(to_unsigned(31, ram_addr_size)) then
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write(lineBuffer, string'("Result 2: +"));
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writeline(output, lineBuffer);
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else
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write(lineBuffer, string'("Result 2: -"));
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writeline(output, lineBuffer);
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end if;
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-- Case 3: hold
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write(lineBuffer, string'("Testing Case 3: "));
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writeline(output, lineBuffer);
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en_pc <= std_logic_vector(to_unsigned(0, 1));
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doJump <= std_logic_vector(to_unsigned(0, 1));
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addr_calc <= std_logic_vector(to_unsigned(90, ram_addr_size));
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wait for 10 ns;
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--same value from
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if addr = std_logic_vector(to_unsigned(31, ram_addr_size)) then
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write(lineBuffer, string'("Result 3: +"));
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writeline(output, lineBuffer);
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else
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write(lineBuffer, string'("Result 3: -"));
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writeline(output, lineBuffer);
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end if;
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-- I'm still waiting
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wait;
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end process;
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end testing;
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