From 30559c81a9d3d9e266da22dc4d84c702869d7edd Mon Sep 17 00:00:00 2001
From: yannickreiss <yannick.reiss@protonmail.ch>
Date: Tue, 26 Sep 2023 20:42:36 +0200
Subject: [PATCH] Implementation of branch, excluding stack

---
 fpga/src/bfpu.vhd   | 36 +++++++++++++++++-
 fpga/src/branch.vhd | 90 +++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 124 insertions(+), 2 deletions(-)

diff --git a/fpga/src/bfpu.vhd b/fpga/src/bfpu.vhd
index 6f0936f..848bc00 100644
--- a/fpga/src/bfpu.vhd
+++ b/fpga/src/bfpu.vhd
@@ -70,9 +70,23 @@ architecture arch of bfpu is
         );
     end component;
 
+    component branch
+        port(
+            clk	        :	in	std_logic;
+		    instruction	:	in	std_logic_vector(2 downto 0);
+		    instr_addr	:	in	std_logic_vector(7 downto 0);
+            cell_value  :   in  std_logic_vector(7 downto 0);
+
+            skip        :   out std_logic;
+		    pc_enable	:	out	std_logic;
+		    pc_out	    :   out	std_logic_vector(7 downto 0)
+        );
+    end component;
+
     signal s_clk            :   std_logic;
     signal s_instrAddr      :   std_logic_vector(7 downto 0);
     signal s_instruction    :   std_logic_vector(2 downto 0);
+    signal s_instrAddr_branch : std_logic_vector(7 downto 0);
 
     signal s_cell_out       :   std_logic_vector(7 downto 0);
     signal s_cell_in        :   std_logic_vector(7 downto 0);
@@ -86,6 +100,10 @@ architecture arch of bfpu is
     signal s_jmp_pc         :   std_logic;
     signal s_jmp_addr_pc    :   std_logic_vector(7 downto 0);
 
+    signal s_skip           :   std_logic;
+    signal s_enable_cells_o :   std_logic;
+    signal s_enable_ptr_o   :   std_logic;
+
 begin
 
     s_clk <= clk;
@@ -106,8 +124,8 @@ begin
 
         new_cell	=>	s_cell_in,
         new_pointer	=>	s_ptr_in,
-        enable_cell	=>	s_enable_cells,
-        enable_ptr	=>	s_enable_ptr,
+        enable_cell	=>	s_enable_cells_o,
+        enable_ptr	=>	s_enable_ptr_o,
         extern_out	=>  led
     );
 
@@ -137,4 +155,18 @@ begin
         pc_out  => s_instrAddr
     );
 
+    branch_bf : branch
+    port map(
+        clk         => s_clk,
+        instruction => s_instruction,
+        instr_addr  => s_instrAddr,
+        cell_value  => s_cell_out,
+        skip        => s_skip,
+        pc_enable   => s_enable_pc,
+        pc_out      => s_instrAddr_branch
+    );
+
+    s_enable_ptr    <= s_skip and s_enable_ptr_o;
+    s_enable_cells  <= s_skip and s_enable_cells_o;
+
 end arch;
diff --git a/fpga/src/branch.vhd b/fpga/src/branch.vhd
index e69de29..e4e6dbc 100644
--- a/fpga/src/branch.vhd
+++ b/fpga/src/branch.vhd
@@ -0,0 +1,90 @@
+-- branch.vhd
+-- Created on: Di 26. Sep 13:47:51 CEST 2023
+-- Author(s): Yannick Reiss <yannick.reiss@protonmail.ch>
+-- Content: Branch unit / ALU for program counter XD
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+-- Entity branch: branch
+entity branch is
+    port(
+        clk	        :	in	std_logic;
+		instruction	:	in	std_logic_vector(2 downto 0);
+		instr_addr	:	in	std_logic_vector(7 downto 0);
+        cell_value  :   in  std_logic_vector(7 downto 0);
+
+        skip        :   out std_logic;
+		pc_enable	:	out	std_logic;
+		pc_out	    :   out	std_logic_vector(7 downto 0)
+    );
+end branch;
+
+-- Architecture impl of branch:
+architecture impl of branch is
+    type stack is array(0 to 255) of std_logic_vector(7 downto 0);
+
+    signal addr_stack       : stack := (others => (others => '0'));
+    signal nested           : std_logic_vector(7 downto 0) := (others => '0'); -- count nested loops
+    signal jump_destination : std_logic_vector(7 downto 0);
+    signal skip_internal    : std_logic := '0';
+    signal stack_ptr        : std_logic_vector(7 downto 0) := (others => '0');
+    signal push_state       : std_logic;
+
+begin
+
+    -- Process p_skip: set skip to true
+    p_skip : process (clk)
+    begin
+        if rising_edge(clk) then
+            if instruction = "110" and unsigned(cell_value) = 0 and unsigned(nested) = 0 and skip_internal = '0' then
+                skip_internal <= '1';
+            end if;
+        end if;
+    end process;
+    
+    -- Process p_continue: set skip to false
+    p_continue : process (clk)
+    begin
+        if rising_edge(clk) then
+            if instruction = "111" and unsigned(nested) = 0 and skip_internal = '1' then
+                skip_internal <= '0';
+            end if;
+        end if;
+    end process;
+    
+    -- Process p_nest : raise nest by one as [ is passed
+    p_nest : process (clk)
+    begin
+        if rising_edge(clk) then
+            if instruction = "110" and skip_internal = '1' then
+                nested <= std_logic_vector(unsigned(nested) + 1);
+            end if;
+        end if;
+    end process;
+    
+    -- Process p_unnest : lower nest, as ] is passed
+    p_unnest : process (clk)
+    begin
+        if rising_edge(clk) then
+            if instruction = "111" and unsigned(nested) > 0 and skip_internal = '1' then
+                nested <= std_logic_vector(unsigned(nested) - 1);
+            end if;
+        end if;
+    end process;
+    
+    -- Process p_push : raise stack and push address
+    p_push : process (clk)
+    begin
+        -- TODO: Implement
+    end process;
+    
+    -- Process p_pop : read address to jump address and lower stack
+    p_pop : process (clk)
+    begin
+        -- TODO: Implement
+    end process;
+    
+    skip <= skip_internal;
+
+end impl;