From 09183f43e170d301c91fab6e50f9a8c893e985b5 Mon Sep 17 00:00:00 2001 From: yannickreiss Date: Sat, 23 Sep 2023 16:10:01 +0200 Subject: [PATCH 01/16] minor changes for memory safety. --- bfpcompiler/src/compilefuck.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/bfpcompiler/src/compilefuck.c b/bfpcompiler/src/compilefuck.c index 481a87e..7a3d0a6 100644 --- a/bfpcompiler/src/compilefuck.c +++ b/bfpcompiler/src/compilefuck.c @@ -18,17 +18,12 @@ int main (int argc, char** argv) { char* filename_compiled = "brainfuck.bin"; - /* check for right amount of cl arguments (even number of arguments (including environment variable)) */ - if (argc % 2) { - exit(EXIT_FAILURE); - } - /* Parse arguments */ char* filename; char* device = "logisim"; for (int i = 1; i < argc; i++) { - if (argv[i][0] == '-') { + if (argv[i][0] == '-' && ((i+1) < argc)) { switch (argv[i][1]) { case 'o': filename_compiled = argv[i+1];break; case 'd': device = argv[i+1];break; From e0c71164866b4ebdf10b6d5fa792365e04061510 Mon Sep 17 00:00:00 2001 From: yannickreiss Date: Sat, 23 Sep 2023 16:10:26 +0200 Subject: [PATCH 02/16] Proof of memory safety in main function. --- bfpcompiler/proof.md | 87 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 bfpcompiler/proof.md diff --git a/bfpcompiler/proof.md b/bfpcompiler/proof.md new file mode 100644 index 0000000..45a43b9 --- /dev/null +++ b/bfpcompiler/proof.md @@ -0,0 +1,87 @@ +# Proof that the compiler is working correctly + +## The compiler is memory safe for all arguments and files. + +The proof is partly inductive and therefore divided in multiple parts. + +### Token extraction + +### Code Analysis + +### Assembling + +### Compiling program + +The memory safety is endangered on two ways. + +1. Addressing unallocated memory in arrays, or based on pointers +2. Copying a pointer and change the values + +#### Addressing unallocated memory + +The first way is only possible in the parsing step of the command line arguments. + +They are parsed in the following loop. + +```c +for (int i = 1; i < argc; i++) { + if (argv[i][0] == '-' && ((i+1) < argc)) { + switch (argv[i][1]) { + case 'o': filename_compiled = argv[i+1];break; + case 'd': device = argv[i+1];break; + default: printf("ERROR: unknown argument: %c\n", argv[i][1]);exit(EXIT_FAILURE); + } + i++; + } else { + filename = argv[i]; + break; + } +} +``` + +The allowed range of the index is $(0, argc-1)$. +Note: The values $0$ and $argc-1$ are included. +In the loop, argv is indexed by i under the condition $0 < i < argc$ and $i+1$ with the additional condition $(i+1) < argc$. + +The variable i is only incremented starting at 1. +This means, the lower border is always right. +The variable can't be raised higher than $argc-1$, +so the upper border can't be reached by i itself. +To avoid accessing undefined memory with $i+1$, +the value of $i+1$ is compared to argc and can't violate memory access. +Through this conditional constraints, the loop can be considered memory safe. + +#### Changing the values of a cell accessed by multiple pointers + +To identify memory leaks through assignment of the same address to multiple pointers, the manually allocated variables in the code are examined for such occasions and then for resulting errors: + +|Variable name|Mutability| +|---|---| +|argv*|| +|filename_compiled|reassigned, values immutable| +|filename|reassigned, values immutable| +|device|reassigned, values immutable| +|fd|reassigned, values immutable| +|buffer|expanded, writing values| +|tokens|reassigned, values immutable| +|binary|| +|fout|reassigned, values immutable| + +As suggested by the table above, the most pointers are just reassigned to a new space. +Even if connected to each other, none of them is changing the values in the addressed memory cells. +Only the buffer is changed, when filled with the content from the file with name *filename*. +As the buffer is not interfering with any other pointer, it can be considered memory safe. + +This means, the main-function, and therefore the entire program, is memory safe if, as shown earlier, the argument-parsing loop and the functions + +- extractTokens +- analyze +- assemble + +are implemented memory safe. + +## Every program, which is accepted by the compiler without error is working on the processor. + +## The compiled binaries are working the same way as the provided code. + +## The compiler is detecting any wrong argument or code. \ No newline at end of file From 61baa3ebfc1314ef720b8b3b7c09ae208fc1385d Mon Sep 17 00:00:00 2001 From: yannickreiss Date: Sun, 24 Sep 2023 08:51:16 +0200 Subject: [PATCH 03/16] Proof --- bfpcompiler/proof.md | 2 -- 1 file changed, 2 deletions(-) diff --git a/bfpcompiler/proof.md b/bfpcompiler/proof.md index 45a43b9..dbc3e96 100644 --- a/bfpcompiler/proof.md +++ b/bfpcompiler/proof.md @@ -83,5 +83,3 @@ are implemented memory safe. ## Every program, which is accepted by the compiler without error is working on the processor. ## The compiled binaries are working the same way as the provided code. - -## The compiler is detecting any wrong argument or code. \ No newline at end of file From b02be01de101d3fb8b4dc1448f407e5661927ee3 Mon Sep 17 00:00:00 2001 From: yannickreiss Date: Tue, 26 Sep 2023 07:26:17 +0200 Subject: [PATCH 04/16] Add files for fpga --- fpga/src/alu.vhd | 0 fpga/src/bfpu.vhd | 0 fpga/src/branch.vhd | 0 fpga/src/cellMemory.vhd | 0 fpga/src/decoder.vhd | 0 fpga/src/instructionMemory.vhd | 0 fpga/src/memoryPointer.vhd | 0 fpga/src/programCounter.vhd | 0 8 files changed, 0 insertions(+), 0 deletions(-) create mode 100644 fpga/src/alu.vhd create mode 100644 fpga/src/bfpu.vhd create mode 100644 fpga/src/branch.vhd create mode 100644 fpga/src/cellMemory.vhd create mode 100644 fpga/src/decoder.vhd create mode 100644 fpga/src/instructionMemory.vhd create mode 100644 fpga/src/memoryPointer.vhd create mode 100644 fpga/src/programCounter.vhd diff --git a/fpga/src/alu.vhd b/fpga/src/alu.vhd new file mode 100644 index 0000000..e69de29 diff --git a/fpga/src/bfpu.vhd b/fpga/src/bfpu.vhd new file mode 100644 index 0000000..e69de29 diff --git a/fpga/src/branch.vhd b/fpga/src/branch.vhd new file mode 100644 index 0000000..e69de29 diff --git a/fpga/src/cellMemory.vhd b/fpga/src/cellMemory.vhd new file mode 100644 index 0000000..e69de29 diff --git a/fpga/src/decoder.vhd b/fpga/src/decoder.vhd new file mode 100644 index 0000000..e69de29 diff --git a/fpga/src/instructionMemory.vhd b/fpga/src/instructionMemory.vhd new file mode 100644 index 0000000..e69de29 diff --git a/fpga/src/memoryPointer.vhd b/fpga/src/memoryPointer.vhd new file mode 100644 index 0000000..e69de29 diff --git a/fpga/src/programCounter.vhd b/fpga/src/programCounter.vhd new file mode 100644 index 0000000..e69de29 From a8d8a4171a5eb226bd20f5ec03349a983283424b Mon Sep 17 00:00:00 2001 From: yannickreiss Date: Tue, 26 Sep 2023 07:27:03 +0200 Subject: [PATCH 05/16] Add constraints file --- fpga/constrainits.xdc | 721 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 721 insertions(+) create mode 100755 fpga/constrainits.xdc diff --git a/fpga/constrainits.xdc b/fpga/constrainits.xdc new file mode 100755 index 0000000..632ff73 --- /dev/null +++ b/fpga/constrainits.xdc @@ -0,0 +1,721 @@ +## This file is a general .xdc for the Nexys4 rev B board +## To use it in a project: +## - uncomment the lines corresponding to used pins +## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project + +## Clock signal +##Bank = 35, Pin name = IO_L12P_T1_MRCC_35, Sch Wname = CLK100MHZ +set_property PACKAGE_PIN E3 [get_ports clk] + set_property IOSTANDARD LVCMOS33 [get_ports clk] + create_clock -add -name clk -period 10.00 -waveform {0 5} [get_ports clk] + +## Switches +##Bank = 34, Pin name = IO_L21P_T3_DQS_34, Sch name = SW0 + set_property PACKAGE_PIN U9 [get_ports {sw[0]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}] +##Bank = 34, Pin name = IO_25_34, Sch name = SW1 +set_property PACKAGE_PIN U8 [get_ports {sw[1]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}] +##Bank = 34, Pin name = IO_L23P_T3_34, Sch name = SW2 +set_property PACKAGE_PIN R7 [get_ports {sw[2]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}] +##Bank = 34, Pin name = IO_L19P_T3_34, Sch name = SW3 +set_property PACKAGE_PIN R6 [get_ports {sw[3]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}] +##Bank = 34, Pin name = IO_L19N_T3_VREF_34, Sch name = SW4 +set_property PACKAGE_PIN R5 [get_ports {sw[4]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}] +##Bank = 34, Pin name = IO_L20P_T3_34, Sch name = SW5 +set_property PACKAGE_PIN V7 [get_ports {sw[5]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}] +##Bank = 34, Pin name = IO_L20N_T3_34, Sch name = SW6 +set_property PACKAGE_PIN V6 [get_ports {sw[6]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}] +##Bank = 34, Pin name = IO_L10P_T1_34, Sch name = SW7 +set_property PACKAGE_PIN V5 [get_ports {sw[7]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}] +##Bank = 34, Pin name = IO_L8P_T1-34, Sch name = SW8 +set_property PACKAGE_PIN U4 [get_ports {sw[8]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}] +##Bank = 34, Pin name = IO_L9N_T1_DQS_34, Sch name = SW9 +set_property PACKAGE_PIN V2 [get_ports {sw[9]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}] +##Bank = 34, Pin name = IO_L9P_T1_DQS_34, Sch name = SW10 +set_property PACKAGE_PIN U2 [get_ports {sw[10]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}] +##Bank = 34, Pin name = IO_L11N_T1_MRCC_34, Sch name = SW11 +set_property PACKAGE_PIN T3 [get_ports {sw[11]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}] +##Bank = 34, Pin name = IO_L17N_T2_34, Sch name = SW12 +set_property PACKAGE_PIN T1 [get_ports {sw[12]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}] +##Bank = 34, Pin name = IO_L11P_T1_SRCC_34, Sch name = SW13 +set_property PACKAGE_PIN R3 [get_ports {sw[13]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}] +##Bank = 34, Pin name = IO_L14N_T2_SRCC_34, Sch name = SW14 +set_property PACKAGE_PIN P3 [get_ports {sw[14]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}] +##Bank = 34, Pin name = IO_L14P_T2_SRCC_34, Sch name = SW15 +set_property PACKAGE_PIN P4 [get_ports {sw[15]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}] + + + +## LEDs +##Bank = 34, Pin name = IO_L24N_T3_34, Sch name = LED0 +set_property PACKAGE_PIN T8 [get_ports {led[0]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}] +#Bank = 34, Pin name = IO_L21N_T3_DQS_34, Sch name = LED1 +set_property PACKAGE_PIN V9 [get_ports {led[1]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}] +#Bank = 34, Pin name = IO_L24P_T3_34, Sch name = LED2 + set_property PACKAGE_PIN R8 [get_ports {led[2]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}] +#Bank = 34, Pin name = IO_L23N_T3_34, Sch name = LED3 + set_property PACKAGE_PIN T6 [get_ports {led[3]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}] +#Bank = 34, Pin name = IO_L12P_T1_MRCC_34, Sch name = LED4 +set_property PACKAGE_PIN T5 [get_ports {led[4]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}] +#Bank = 34, Pin name = IO_L12N_T1_MRCC_34, Sch name = LED5 +set_property PACKAGE_PIN T4 [get_ports {led[5]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}] +#Bank = 34, Pin name = IO_L22P_T3_34, Sch name = LED6 +set_property PACKAGE_PIN U7 [get_ports {led[6]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}] +#Bank = 34, Pin name = IO_L22N_T3_34, Sch name = LED7 +set_property PACKAGE_PIN U6 [get_ports {led[7]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}] +##Bank = 34, Pin name = IO_L10N_T1_34, Sch name = LED8 +set_property PACKAGE_PIN V4 [get_ports {led[8]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}] +##Bank = 34, Pin name = IO_L8N_T1_34, Sch name = LED9 +set_property PACKAGE_PIN U3 [get_ports {led[9]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}] +##Bank = 34, Pin name = IO_L7N_T1_34, Sch name = LED10 +set_property PACKAGE_PIN V1 [get_ports {led[10]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}] +##Bank = 34, Pin name = IO_L17P_T2_34, Sch name = LED11 +set_property PACKAGE_PIN R1 [get_ports {led[11]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}] +##Bank = 34, Pin name = IO_L13N_T2_MRCC_34, Sch name = LED12 +set_property PACKAGE_PIN P5 [get_ports {led[12]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}] +##Bank = 34, Pin name = IO_L7P_T1_34, Sch name = LED13 +set_property PACKAGE_PIN U1 [get_ports {led[13]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}] +##Bank = 34, Pin name = IO_L15N_T2_DQS_34, Sch name = LED14 +set_property PACKAGE_PIN R2 [get_ports {led[14]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}] +##Bank = 34, Pin name = IO_L15P_T2_DQS_34, Sch name = LED15 +set_property PACKAGE_PIN P2 [get_ports {led[15]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}] + +##Bank = 34, Pin name = IO_L5P_T0_34, Sch name = LED16_R +set_property PACKAGE_PIN K5 [get_ports {rgb[0]}] + set_property IOSTANDARD LVCMOS33 [get_ports {rgb[0]}] +##Bank = 15, Pin name = IO_L5P_T0_AD9P_15, Sch name = LED16_G +set_property PACKAGE_PIN F13 [get_ports {rgb[1]}] + set_property IOSTANDARD LVCMOS33 [get_ports {rgb[1]}] +##Bank = 35, Pin name = IO_L19N_T3_VREF_35, Sch name = LED16_B +set_property PACKAGE_PIN F6 [get_ports {rgb[2]}] + set_property IOSTANDARD LVCMOS33 [get_ports {rgb[2]}] +##Bank = 34, Pin name = IO_0_34, Sch name = LED17_R +set_property PACKAGE_PIN K6 [get_ports {rgb[3]}] + set_property IOSTANDARD LVCMOS33 [get_ports {rgb[3]}] +##Bank = 35, Pin name = IO_24P_T3_35, Sch name = LED17_G +set_property PACKAGE_PIN H6 [get_ports {rgb[4]}] + set_property IOSTANDARD LVCMOS33 [get_ports {rgb[4]}] +##Bank = CONFIG, Pin name = IO_L3N_T0_DQS_EMCCLK_14, Sch name = LED17_B +set_property PACKAGE_PIN L16 [get_ports {rgb[5]}] + set_property IOSTANDARD LVCMOS33 [get_ports {rgb[5]}] + + + +##7 segment display +##Bank = 34, Pin name = IO_L2N_T0_34, Sch name = CA +#set_property PACKAGE_PIN L3 [get_ports {seg[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}] +##Bank = 34, Pin name = IO_L3N_T0_DQS_34, Sch name = CB +#set_property PACKAGE_PIN N1 [get_ports {seg[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}] +##Bank = 34, Pin name = IO_L6N_T0_VREF_34, Sch name = CC +#set_property PACKAGE_PIN L5 [get_ports {seg[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}] +##Bank = 34, Pin name = IO_L5N_T0_34, Sch name = CD +#set_property PACKAGE_PIN L4 [get_ports {seg[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}] +##Bank = 34, Pin name = IO_L2P_T0_34, Sch name = CE +#set_property PACKAGE_PIN K3 [get_ports {seg[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}] +##Bank = 34, Pin name = IO_L4N_T0_34, Sch name = CF +#set_property PACKAGE_PIN M2 [get_ports {seg[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}] +##Bank = 34, Pin name = IO_L6P_T0_34, Sch name = CG +#set_property PACKAGE_PIN L6 [get_ports {seg[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}] + +##Bank = 34, Pin name = IO_L16P_T2_34, Sch name = DP +#set_property PACKAGE_PIN M4 [get_ports dp] + #set_property IOSTANDARD LVCMOS33 [get_ports dp] + +##Bank = 34, Pin name = IO_L18N_T2_34, Sch name = AN0 +#set_property PACKAGE_PIN N6 [get_ports {an[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}] +##Bank = 34, Pin name = IO_L18P_T2_34, Sch name = AN1 +#set_property PACKAGE_PIN M6 [get_ports {an[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}] +##Bank = 34, Pin name = IO_L4P_T0_34, Sch name = AN2 +#set_property PACKAGE_PIN M3 [get_ports {an[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}] +##Bank = 34, Pin name = IO_L13_T2_MRCC_34, Sch name = AN3 +#set_property PACKAGE_PIN N5 [get_ports {an[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}] +##Bank = 34, Pin name = IO_L3P_T0_DQS_34, Sch name = AN4 +#set_property PACKAGE_PIN N2 [get_ports {an[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {an[4]}] +##Bank = 34, Pin name = IO_L16N_T2_34, Sch name = AN5 +#set_property PACKAGE_PIN N4 [get_ports {an[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {an[5]}] +##Bank = 34, Pin name = IO_L1P_T0_34, Sch name = AN6 +#set_property PACKAGE_PIN L1 [get_ports {an[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {an[6]}] +##Bank = 34, Pin name = IO_L1N_T034, Sch name = AN7 +#set_property PACKAGE_PIN M1 [get_ports {an[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {an[7]}] + + + +##Buttons +##Bank = 15, Pin name = IO_L3P_T0_DQS_AD1P_15, Sch name = CPU_RESET +set_property PACKAGE_PIN C12 [get_ports reset] + set_property IOSTANDARD LVCMOS33 [get_ports reset] +##Bank = 15, Pin name = IO_L11N_T1_SRCC_15, Sch name = BTNC +#set_property PACKAGE_PIN E16 [get_ports clk] +# set_property IOSTANDARD LVCMOS33 [get_ports clk] +##Bank = 15, Pin name = IO_L14P_T2_SRCC_15, Sch name = BTNU +#set_property PACKAGE_PIN F15 [get_ports btnU] + #set_property IOSTANDARD LVCMOS33 [get_ports btnU] +##Bank = CONFIG, Pin name = IO_L15N_T2_DQS_DOUT_CSO_B_14, Sch name = BTNL +#set_property PACKAGE_PIN T16 [get_ports btnL] + #set_property IOSTANDARD LVCMOS33 [get_ports btnL] +##Bank = 14, Pin name = IO_25_14, Sch name = BTNR +#set_property PACKAGE_PIN R10 [get_ports btnR] + #set_property IOSTANDARD LVCMOS33 [get_ports btnR] +##Bank = 14, Pin name = IO_L21P_T3_DQS_14, Sch name = BTND +#set_property PACKAGE_PIN V10 [get_ports btnD] + #set_property IOSTANDARD LVCMOS33 [get_ports btnD] + + + +##Pmod Header JA +##Bank = 15, Pin name = IO_L1N_T0_AD0N_15, Sch name = JA1 +#set_property PACKAGE_PIN B13 [get_ports {JA[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}] +##Bank = 15, Pin name = IO_L5N_T0_AD9N_15, Sch name = JA2 +#set_property PACKAGE_PIN F14 [get_ports {JA[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}] +##Bank = 15, Pin name = IO_L16N_T2_A27_15, Sch name = JA3 +#set_property PACKAGE_PIN D17 [get_ports {JA[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}] +##Bank = 15, Pin name = IO_L16P_T2_A28_15, Sch name = JA4 +#set_property PACKAGE_PIN E17 [get_ports {JA[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}] +##Bank = 15, Pin name = IO_0_15, Sch name = JA7 +#set_property PACKAGE_PIN G13 [get_ports {JA[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}] +##Bank = 15, Pin name = IO_L20N_T3_A19_15, Sch name = JA8 +#set_property PACKAGE_PIN C17 [get_ports {JA[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}] +##Bank = 15, Pin name = IO_L21N_T3_A17_15, Sch name = JA9 +#set_property PACKAGE_PIN D18 [get_ports {JA[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}] +##Bank = 15, Pin name = IO_L21P_T3_DQS_15, Sch name = JA10 +#set_property PACKAGE_PIN E18 [get_ports {JA[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}] + + + +##Pmod Header JB +##Bank = 15, Pin name = IO_L15N_T2_DQS_ADV_B_15, Sch name = JB1 +#set_property PACKAGE_PIN G14 [get_ports {JB[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}] +##Bank = 14, Pin name = IO_L13P_T2_MRCC_14, Sch name = JB2 +#set_property PACKAGE_PIN P15 [get_ports {JB[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}] +##Bank = 14, Pin name = IO_L21N_T3_DQS_A06_D22_14, Sch name = JB3 +#set_property PACKAGE_PIN V11 [get_ports {JB[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}] +##Bank = CONFIG, Pin name = IO_L16P_T2_CSI_B_14, Sch name = JB4 +#set_property PACKAGE_PIN V15 [get_ports {JB[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}] +##Bank = 15, Pin name = IO_25_15, Sch name = JB7 +#set_property PACKAGE_PIN K16 [get_ports {JB[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}] +##Bank = CONFIG, Pin name = IO_L15P_T2_DQS_RWR_B_14, Sch name = JB8 +#set_property PACKAGE_PIN R16 [get_ports {JB[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}] +##Bank = 14, Pin name = IO_L24P_T3_A01_D17_14, Sch name = JB9 +#set_property PACKAGE_PIN T9 [get_ports {JB[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}] +##Bank = 14, Pin name = IO_L19N_T3_A09_D25_VREF_14, Sch name = JB10 +#set_property PACKAGE_PIN U11 [get_ports {JB[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}] + + + +##Pmod Header JC +##Bank = 35, Pin name = IO_L23P_T3_35, Sch name = JC1 +#set_property PACKAGE_PIN K2 [get_ports {JC[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}] +##Bank = 35, Pin name = IO_L6P_T0_35, Sch name = JC2 +#set_property PACKAGE_PIN E7 [get_ports {JC[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}] +##Bank = 35, Pin name = IO_L22P_T3_35, Sch name = JC3 +#set_property PACKAGE_PIN J3 [get_ports {JC[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}] +##Bank = 35, Pin name = IO_L21P_T3_DQS_35, Sch name = JC4 +#set_property PACKAGE_PIN J4 [get_ports {JC[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}] +##Bank = 35, Pin name = IO_L23N_T3_35, Sch name = JC7 +#set_property PACKAGE_PIN K1 [get_ports {JC[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}] +##Bank = 35, Pin name = IO_L5P_T0_AD13P_35, Sch name = JC8 +#set_property PACKAGE_PIN E6 [get_ports {JC[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}] +##Bank = 35, Pin name = IO_L22N_T3_35, Sch name = JC9 +#set_property PACKAGE_PIN J2 [get_ports {JC[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}] +##Bank = 35, Pin name = IO_L19P_T3_35, Sch name = JC10 +#set_property PACKAGE_PIN G6 [get_ports {JC[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}] + + + +##Pmod Header JD +##Bank = 35, Pin name = IO_L21N_T2_DQS_35, Sch name = JD1 +#set_property PACKAGE_PIN H4 [get_ports {JD[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JD[0]}] +##Bank = 35, Pin name = IO_L17P_T2_35, Sch name = JD2 +#set_property PACKAGE_PIN H1 [get_ports {JD[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JD[1]}] +##Bank = 35, Pin name = IO_L17N_T2_35, Sch name = JD3 +#set_property PACKAGE_PIN G1 [get_ports {JD[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JD[2]}] +##Bank = 35, Pin name = IO_L20N_T3_35, Sch name = JD4 +#set_property PACKAGE_PIN G3 [get_ports {JD[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JD[3]}] +##Bank = 35, Pin name = IO_L15P_T2_DQS_35, Sch name = JD7 +#set_property PACKAGE_PIN H2 [get_ports {JD[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JD[4]}] +##Bank = 35, Pin name = IO_L20P_T3_35, Sch name = JD8 +#set_property PACKAGE_PIN G4 [get_ports {JD[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JD[5]}] +##Bank = 35, Pin name = IO_L15N_T2_DQS_35, Sch name = JD9 +#set_property PACKAGE_PIN G2 [get_ports {JD[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JD[6]}] +##Bank = 35, Pin name = IO_L13N_T2_MRCC_35, Sch name = JD10 +#set_property PACKAGE_PIN F3 [get_ports {JD[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JD[7]}] + + + +##Pmod Header JXADC +##Bank = 15, Pin name = IO_L9P_T1_DQS_AD3P_15, Sch name = XADC1_P -> XA1_P +#set_property PACKAGE_PIN A13 [get_ports {JXADC[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}] +##Bank = 15, Pin name = IO_L8P_T1_AD10P_15, Sch name = XADC2_P -> XA2_P +#set_property PACKAGE_PIN A15 [get_ports {JXADC[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}] +##Bank = 15, Pin name = IO_L7P_T1_AD2P_15, Sch name = XADC3_P -> XA3_P +#set_property PACKAGE_PIN B16 [get_ports {JXADC[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}] +##Bank = 15, Pin name = IO_L10P_T1_AD11P_15, Sch name = XADC4_P -> XA4_P +#set_property PACKAGE_PIN B18 [get_ports {JXADC[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}] +##Bank = 15, Pin name = IO_L9N_T1_DQS_AD3N_15, Sch name = XADC1_N -> XA1_N +#set_property PACKAGE_PIN A14 [get_ports {JXADC[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}] +##Bank = 15, Pin name = IO_L8N_T1_AD10N_15, Sch name = XADC2_N -> XA2_N +#set_property PACKAGE_PIN A16 [get_ports {JXADC[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}] +##Bank = 15, Pin name = IO_L7N_T1_AD2N_15, Sch name = XADC3_N -> XA3_N +#set_property PACKAGE_PIN B17 [get_ports {JXADC[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}] +##Bank = 15, Pin name = IO_L10N_T1_AD11N_15, Sch name = XADC4_N -> XA4_N +#set_property PACKAGE_PIN A18 [get_ports {JXADC[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}] + + + +##VGA Connector +##Bank = 35, Pin name = IO_L8N_T1_AD14N_35, Sch name = VGA_R0 +set_property PACKAGE_PIN A3 [get_ports {vgaRed[0]}] + set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}] +##Bank = 35, Pin name = IO_L7N_T1_AD6N_35, Sch name = VGA_R1 +set_property PACKAGE_PIN B4 [get_ports {vgaRed[1]}] + set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}] +##Bank = 35, Pin name = IO_L1N_T0_AD4N_35, Sch name = VGA_R2 +set_property PACKAGE_PIN C5 [get_ports {vgaRed[2]}] + set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}] +##Bank = 35, Pin name = IO_L8P_T1_AD14P_35, Sch name = VGA_R3 +#set_property PACKAGE_PIN A4 [get_ports {vgaRed[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}] +##Bank = 35, Pin name = IO_L2P_T0_AD12P_35, Sch name = VGA_B0 +set_property PACKAGE_PIN B7 [get_ports {vgaBlue[0]}] + set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}] +##Bank = 35, Pin name = IO_L4N_T0_35, Sch name = VGA_B1 +set_property PACKAGE_PIN C7 [get_ports {vgaBlue[1]}] + set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}] +##Bank = 35, Pin name = IO_L6N_T0_VREF_35, Sch name = VGA_B2 +set_property PACKAGE_PIN D7 [get_ports {vgaBlue[2]}] + set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}] +##Bank = 35, Pin name = IO_L4P_T0_35, Sch name = VGA_B3 +#set_property PACKAGE_PIN D8 [get_ports {vgaBlue[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}] +##Bank = 35, Pin name = IO_L1P_T0_AD4P_35, Sch name = VGA_G0 +set_property PACKAGE_PIN C6 [get_ports {vgaGreen[0]}] + set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}] +##Bank = 35, Pin name = IO_L3N_T0_DQS_AD5N_35, Sch name = VGA_G1 +set_property PACKAGE_PIN A5 [get_ports {vgaGreen[1]}] + set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}] +##Bank = 35, Pin name = IO_L2N_T0_AD12N_35, Sch name = VGA_G2 +#set_property PACKAGE_PIN B6 [get_ports {vgaGreen[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}] +##Bank = 35, Pin name = IO_L3P_T0_DQS_AD5P_35, Sch name = VGA_G3 +#set_property PACKAGE_PIN A6 [get_ports {vgaGreen[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}] +##Bank = 15, Pin name = IO_L4P_T0_15, Sch name = VGA_HS +set_property PACKAGE_PIN B11 [get_ports Hsync] + set_property IOSTANDARD LVCMOS33 [get_ports Hsync] +##Bank = 15, Pin name = IO_L3N_T0_DQS_AD1N_15, Sch name = VGA_VS +set_property PACKAGE_PIN B12 [get_ports Vsync] + set_property IOSTANDARD LVCMOS33 [get_ports Vsync] + + + +##Micro SD Connector +##Bank = 35, Pin name = IO_L14P_T2_SRCC_35, Sch name = SD_RESET +#set_property PACKAGE_PIN E2 [get_ports sdReset] + #set_property IOSTANDARD LVCMOS33 [get_ports sdReset] +##Bank = 35, Pin name = IO_L9N_T1_DQS_AD7N_35, Sch name = SD_CD +#set_property PACKAGE_PIN A1 [get_ports sdCD] + #set_property IOSTANDARD LVCMOS33 [get_ports sdCD] +##Bank = 35, Pin name = IO_L9P_T1_DQS_AD7P_35, Sch name = SD_SCK +#set_property PACKAGE_PIN B1 [get_ports sdSCK] + #set_property IOSTANDARD LVCMOS33 [get_ports sdSCK] +##Bank = 35, Pin name = IO_L16N_T2_35, Sch name = SD_CMD +#set_property PACKAGE_PIN C1 [get_ports sdCmd] + #set_property IOSTANDARD LVCMOS33 [get_ports sdCmd] +##Bank = 35, Pin name = IO_L16P_T2_35, Sch name = SD_DAT0 +#set_property PACKAGE_PIN C2 [get_ports {sdData[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sdData[0]}] +##Bank = 35, Pin name = IO_L18N_T2_35, Sch name = SD_DAT1 +#set_property PACKAGE_PIN E1 [get_ports {sdData[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sdData[1]}] +##Bank = 35, Pin name = IO_L18P_T2_35, Sch name = SD_DAT2 +#set_property PACKAGE_PIN F1 [get_ports {sdData[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sdData[2]}] +##Bank = 35, Pin name = IO_L14N_T2_SRCC_35, Sch name = SD_DAT3 +#set_property PACKAGE_PIN D2 [get_ports {sdData[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sdData[3]}] + + + +##Accelerometer +##Bank = 15, Pin name = IO_L6N_T0_VREF_15, Sch name = ACL_MISO +#set_property PACKAGE_PIN D13 [get_ports MISO] +# set_property IOSTANDARD LVCMOS33 [get_ports MISO] +#Bank = 15, Pin name = IO_L2N_T0_AD8N_15, Sch name = ACL_MOSI +#set_property PACKAGE_PIN B14 [get_ports MOSI] +# set_property IOSTANDARD LVCMOS33 [get_ports MOSI] +#Bank = 15, Pin name = IO_L12P_T1_MRCC_15, Sch name = ACL_SCLK +#set_property PACKAGE_PIN D15 [get_ports SCLK] +# set_property IOSTANDARD LVCMOS33 [get_ports SCLK] +#Bank = 15, Pin name = IO_L12N_T1_MRCC_15, Sch name = ACL_CSN +#set_property PACKAGE_PIN C15 [get_ports SS] +# set_property IOSTANDARD LVCMOS33 [get_ports SS] +##Bank = 15, Pin name = IO_L20P_T3_A20_15, Sch name = ACL_INT1 +#set_property PACKAGE_PIN C16 [get_ports aclInt1] + #set_property IOSTANDARD LVCMOS33 [get_ports aclInt1] +##Bank = 15, Pin name = IO_L11P_T1_SRCC_15, Sch name = ACL_INT2 +#set_property PACKAGE_PIN E15 [get_ports aclInt2] + #set_property IOSTANDARD LVCMOS33 [get_ports aclInt2] + + + +##Temperature Sensor +##Bank = 15, Pin name = IO_L14N_T2_SRCC_15, Sch name = TMP_SCL +#set_property PACKAGE_PIN F16 [get_ports tmpSCL] + #set_property IOSTANDARD LVCMOS33 [get_ports tmpSCL] +##Bank = 15, Pin name = IO_L13N_T2_MRCC_15, Sch name = TMP_SDA +#set_property PACKAGE_PIN G16 [get_ports tmpSDA] + #set_property IOSTANDARD LVCMOS33 [get_ports tmpSDA] +##Bank = 15, Pin name = IO_L1P_T0_AD0P_15, Sch name = TMP_INT +#set_property PACKAGE_PIN D14 [get_ports tmpInt] + #set_property IOSTANDARD LVCMOS33 [get_ports tmpInt] +##Bank = 15, Pin name = IO_L1N_T0_AD0N_15, Sch name = TMP_CT +#set_property PACKAGE_PIN C14 [get_ports tmpCT] + #set_property IOSTANDARD LVCMOS33 [get_ports tmpCT] + + + +##Omnidirectional Microphone +##Bank = 35, Pin name = IO_25_35, Sch name = M_CLK +#set_property PACKAGE_PIN J5 [get_ports micClk] + #set_property IOSTANDARD LVCMOS33 [get_ports micClk] +##Bank = 35, Pin name = IO_L24N_T3_35, Sch name = M_DATA +#set_property PACKAGE_PIN H5 [get_ports micData] + #set_property IOSTANDARD LVCMOS33 [get_ports micData] +##Bank = 35, Pin name = IO_0_35, Sch name = M_LRSEL +#set_property PACKAGE_PIN F5 [get_ports micLRSel] + #set_property IOSTANDARD LVCMOS33 [get_ports micLRSel] + + + +##PWM Audio Amplifier +##Bank = 15, Pin name = IO_L4N_T0_15, Sch name = AUD_PWM +#set_property PACKAGE_PIN A11 [get_ports ampPWM] + #set_property IOSTANDARD LVCMOS33 [get_ports ampPWM] +##Bank = 15, Pin name = IO_L6P_T0_15, Sch name = AUD_SD +#set_property PACKAGE_PIN D12 [get_ports ampSD] + #set_property IOSTANDARD LVCMOS33 [get_ports ampSD] + + +##USB-RS232 Interface +##Bank = 35, Pin name = IO_L7P_T1_AD6P_35, Sch name = UART_TXD_IN +#set_property PACKAGE_PIN C4 [get_ports RsRx] + #set_property IOSTANDARD LVCMOS33 [get_ports RsRx] +##Bank = 35, Pin name = IO_L11N_T1_SRCC_35, Sch name = UART_RXD_OUT +#set_property PACKAGE_PIN D4 [get_ports RsTx] + #set_property IOSTANDARD LVCMOS33 [get_ports RsTx] +##Bank = 35, Pin name = IO_L12N_T1_MRCC_35, Sch name = UART_CTS +#set_property PACKAGE_PIN D3 [get_ports RsCts] + #set_property IOSTANDARD LVCMOS33 [get_ports RsCts] +##Bank = 35, Pin name = IO_L5N_T0_AD13N_35, Sch name = UART_RTS +#set_property PACKAGE_PIN E5 [get_ports RsRts] + #set_property IOSTANDARD LVCMOS33 [get_ports RsRts] + + + +##USB HID (PS/2) +##Bank = 35, Pin name = IO_L13P_T2_MRCC_35, Sch name = PS2_CLK +#set_property PACKAGE_PIN F4 [get_ports PS2Clk] + #set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk] + #set_property PULLUP true [get_ports PS2Clk] +##Bank = 35, Pin name = IO_L10N_T1_AD15N_35, Sch name = PS2_DATA +#set_property PACKAGE_PIN B2 [get_ports PS2Data] + #set_property IOSTANDARD LVCMOS33 [get_ports PS2Data] + #set_property PULLUP true [get_ports PS2Data] + + + +##SMSC Ethernet PHY +##Bank = 16, Pin name = IO_L11P_T1_SRCC_16, Sch name = ETH_MDC +#set_property PACKAGE_PIN C9 [get_ports PhyMdc] + #set_property IOSTANDARD LVCMOS33 [get_ports PhyMdc] +##Bank = 16, Pin name = IO_L14N_T2_SRCC_16, Sch name = ETH_MDIO +#set_property PACKAGE_PIN A9 [get_ports PhyMdio] + #set_property IOSTANDARD LVCMOS33 [get_ports PhyMdio] +##Bank = 35, Pin name = IO_L10P_T1_AD15P_35, Sch name = ETH_RSTN +#set_property PACKAGE_PIN B3 [get_ports PhyRstn] + #set_property IOSTANDARD LVCMOS33 [get_ports PhyRstn] +##Bank = 16, Pin name = IO_L6N_T0_VREF_16, Sch name = ETH_CRSDV +#set_property PACKAGE_PIN D9 [get_ports PhyCrs] + #set_property IOSTANDARD LVCMOS33 [get_ports PhyCrs] +##Bank = 16, Pin name = IO_L13N_T2_MRCC_16, Sch name = ETH_RXERR +#set_property PACKAGE_PIN C10 [get_ports PhyRxErr] + #set_property IOSTANDARD LVCMOS33 [get_ports PhyRxErr] +##Bank = 16, Pin name = IO_L19N_T3_VREF_16, Sch name = ETH_RXD0 +#set_property PACKAGE_PIN D10 [get_ports {PhyRxd[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {PhyRxd[0]}] +##Bank = 16, Pin name = IO_L13P_T2_MRCC_16, Sch name = ETH_RXD1 +#set_property PACKAGE_PIN C11 [get_ports {PhyRxd[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {PhyRxd[1]}] +##Bank = 16, Pin name = IO_L11N_T1_SRCC_16, Sch name = ETH_TXEN +#set_property PACKAGE_PIN B9 [get_ports PhyTxEn] + #set_property IOSTANDARD LVCMOS33 [get_ports PhyTxEn] +##Bank = 16, Pin name = IO_L14P_T2_SRCC_16, Sch name = ETH_TXD0 +#set_property PACKAGE_PIN A10 [get_ports {PhyTxd[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {PhyTxd[0]}] +##Bank = 16, Pin name = IO_L12N_T1_MRCC_16, Sch name = ETH_TXD1 +#set_property PACKAGE_PIN A8 [get_ports {PhyTxd[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {PhyTxd[1]}] +##Bank = 35, Pin name = IO_L11P_T1_SRCC_35, Sch name = ETH_REFCLK +#set_property PACKAGE_PIN D5 [get_ports PhyClk50Mhz] + #set_property IOSTANDARD LVCMOS33 [get_ports PhyClk50Mhz] +##Bank = 16, Pin name = IO_L12P_T1_MRCC_16, Sch name = ETH_INTN +#set_property PACKAGE_PIN B8 [get_ports PhyIntn] + #set_property IOSTANDARD LVCMOS33 [get_ports PhyIntn] + + + +##Quad SPI Flash +##Bank = CONFIG, Pin name = CCLK_0, Sch name = QSPI_SCK +#set_property PACKAGE_PIN E9 [get_ports {QspiSCK}] + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiSCK}] +##Bank = CONFIG, Pin name = IO_L1P_T0_D00_MOSI_14, Sch name = QSPI_DQ0 +#set_property PACKAGE_PIN K17 [get_ports {QspiDB[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}] +##Bank = CONFIG, Pin name = IO_L1N_T0_D01_DIN_14, Sch name = QSPI_DQ1 +#set_property PACKAGE_PIN K18 [get_ports {QspiDB[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}] +##Bank = CONFIG, Pin name = IO_L20_T0_D02_14, Sch name = QSPI_DQ2 +#set_property PACKAGE_PIN L14 [get_ports {QspiDB[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}] +##Bank = CONFIG, Pin name = IO_L2P_T0_D03_14, Sch name = QSPI_DQ3 +#set_property PACKAGE_PIN M14 [get_ports {QspiDB[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}] +##Bank = CONFIG, Pin name = IO_L15N_T2_DQS_DOUT_CSO_B_14, Sch name = QSPI_CSN +#set_property PACKAGE_PIN L13 [get_ports QspiCSn] + #set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn] + + + +##Cellular RAM +##Bank = 14, Pin name = IO_L14N_T2_SRCC_14, Sch name = CRAM_CLK +#set_property PACKAGE_PIN T15 [get_ports RamCLK] + #set_property IOSTANDARD LVCMOS33 [get_ports RamCLK] +##Bank = 14, Pin name = IO_L23P_T3_A03_D19_14, Sch name = CRAM_ADVN +#set_property PACKAGE_PIN T13 [get_ports RamADVn] + #set_property IOSTANDARD LVCMOS33 [get_ports RamADVn] +##Bank = 14, Pin name = IO_L4P_T0_D04_14, Sch name = CRAM_CEN +#set_property PACKAGE_PIN L18 [get_ports RamCEn] + #set_property IOSTANDARD LVCMOS33 [get_ports RamCEn] +##Bank = 15, Pin name = IO_L19P_T3_A22_15, Sch name = CRAM_CRE +#set_property PACKAGE_PIN J14 [get_ports RamCRE] + #set_property IOSTANDARD LVCMOS33 [get_ports RamCRE] +##Bank = 15, Pin name = IO_L15P_T2_DQS_15, Sch name = CRAM_OEN +#set_property PACKAGE_PIN H14 [get_ports RamOEn] + #set_property IOSTANDARD LVCMOS33 [get_ports RamOEn] +##Bank = 14, Pin name = IO_0_14, Sch name = CRAM_WEN +#set_property PACKAGE_PIN R11 [get_ports RamWEn] + #set_property IOSTANDARD LVCMOS33 [get_ports RamWEn] +##Bank = 15, Pin name = IO_L24N_T3_RS0_15, Sch name = CRAM_LBN +#set_property PACKAGE_PIN J15 [get_ports RamLBn] + #set_property IOSTANDARD LVCMOS33 [get_ports RamLBn] +##Bank = 15, Pin name = IO_L17N_T2_A25_15, Sch name = CRAM_UBN +#set_property PACKAGE_PIN J13 [get_ports RamUBn] + #set_property IOSTANDARD LVCMOS33 [get_ports RamUBn] +##Bank = 14, Pin name = IO_L14P_T2_SRCC_14, Sch name = CRAM_WAIT +#set_property PACKAGE_PIN T14 [get_ports RamWait] + #set_property IOSTANDARD LVCMOS33 [get_ports RamWait] + +##Bank = 14, Pin name = IO_L5P_T0_DQ06_14, Sch name = CRAM_DQ0 +#set_property PACKAGE_PIN R12 [get_ports {MemDB[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[0]}] +##Bank = 14, Pin name = IO_L19P_T3_A10_D26_14, Sch name = CRAM_DQ1 +#set_property PACKAGE_PIN T11 [get_ports {MemDB[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[1]}] +##Bank = 14, Pin name = IO_L20P_T3_A08)D24_14, Sch name = CRAM_DQ2 +#set_property PACKAGE_PIN U12 [get_ports {MemDB[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[2]}] +##Bank = 14, Pin name = IO_L5N_T0_D07_14, Sch name = CRAM_DQ3 +#set_property PACKAGE_PIN R13 [get_ports {MemDB[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[3]}] +##Bank = 14, Pin name = IO_L17N_T2_A13_D29_14, Sch name = CRAM_DQ4 +#set_property PACKAGE_PIN U18 [get_ports {MemDB[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[4]}] +##Bank = 14, Pin name = IO_L12N_T1_MRCC_14, Sch name = CRAM_DQ5 +#set_property PACKAGE_PIN R17 [get_ports {MemDB[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[5]}] +##Bank = 14, Pin name = IO_L7N_T1_D10_14, Sch name = CRAM_DQ6 +#set_property PACKAGE_PIN T18 [get_ports {MemDB[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[6]}] +##Bank = 14, Pin name = IO_L7P_T1_D09_14, Sch name = CRAM_DQ7 +#set_property PACKAGE_PIN R18 [get_ports {MemDB[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[7]}] +##Bank = 15, Pin name = IO_L22N_T3_A16_15, Sch name = CRAM_DQ8 +#set_property PACKAGE_PIN F18 [get_ports {MemDB[8]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[8]}] +##Bank = 15, Pin name = IO_L22P_T3_A17_15, Sch name = CRAM_DQ9 +#set_property PACKAGE_PIN G18 [get_ports {MemDB[9]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[9]}] +##Bank = 15, Pin name = IO_IO_L18N_T2_A23_15, Sch name = CRAM_DQ10 +#set_property PACKAGE_PIN G17 [get_ports {MemDB[10]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[10]}] +##Bank = 14, Pin name = IO_L4N_T0_D05_14, Sch name = CRAM_DQ11 +#set_property PACKAGE_PIN M18 [get_ports {MemDB[11]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[11]}] +##Bank = 14, Pin name = IO_L10N_T1_D15_14, Sch name = CRAM_DQ12 +#set_property PACKAGE_PIN M17 [get_ports {MemDB[12]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[12]}] +##Bank = 14, Pin name = IO_L9N_T1_DQS_D13_14, Sch name = CRAM_DQ13 +#set_property PACKAGE_PIN P18 [get_ports {MemDB[13]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[13]}] +##Bank = 14, Pin name = IO_L9P_T1_DQS_14, Sch name = CRAM_DQ14 +#set_property PACKAGE_PIN N17 [get_ports {MemDB[14]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[14]}] +##Bank = 14, Pin name = IO_L12P_T1_MRCC_14, Sch name = CRAM_DQ15 +#set_property PACKAGE_PIN P17 [get_ports {MemDB[15]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[15]}] + +##Bank = 15, Pin name = IO_L23N_T3_FWE_B_15, Sch name = CRAM_A0 +#set_property PACKAGE_PIN J18 [get_ports {MemAdr[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[0]}] +##Bank = 15, Pin name = IO_L18P_T2_A24_15, Sch name = CRAM_A1 +#set_property PACKAGE_PIN H17 [get_ports {MemAdr[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[1]}] +##Bank = 15, Pin name = IO_L19N_T3_A21_VREF_15, Sch name = CRAM_A2 +#set_property PACKAGE_PIN H15 [get_ports {MemAdr[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[2]}] +##Bank = 15, Pin name = IO_L23P_T3_FOE_B_15, Sch name = CRAM_A3 +#set_property PACKAGE_PIN J17 [get_ports {MemAdr[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[3]}] +##Bank = 15, Pin name = IO_L13P_T2_MRCC_15, Sch name = CRAM_A4 +#set_property PACKAGE_PIN H16 [get_ports {MemAdr[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[4]}] +##Bank = 15, Pin name = IO_L24P_T3_RS1_15, Sch name = CRAM_A5 +#set_property PACKAGE_PIN K15 [get_ports {MemAdr[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[5]}] +##Bank = 15, Pin name = IO_L17P_T2_A26_15, Sch name = CRAM_A6 +#set_property PACKAGE_PIN K13 [get_ports {MemAdr[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[6]}] +##Bank = 14, Pin name = IO_L11P_T1_SRCC_14, Sch name = CRAM_A7 +#set_property PACKAGE_PIN N15 [get_ports {MemAdr[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[7]}] +##Bank = 14, Pin name = IO_L16N_T2_SRCC-14, Sch name = CRAM_A8 +#set_property PACKAGE_PIN V16 [get_ports {MemAdr[8]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[8]}] +##Bank = 14, Pin name = IO_L22P_T3_A05_D21_14, Sch name = CRAM_A9 +#set_property PACKAGE_PIN U14 [get_ports {MemAdr[9]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[9]}] +##Bank = 14, Pin name = IO_L22N_T3_A04_D20_14, Sch name = CRAM_A10 +#set_property PACKAGE_PIN V14 [get_ports {MemAdr[10]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[10]}] +##Bank = 14, Pin name = IO_L20N_T3_A07_D23_14, Sch name = CRAM_A11 +#set_property PACKAGE_PIN V12 [get_ports {MemAdr[11]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[11]}] +##Bank = 14, Pin name = IO_L8N_T1_D12_14, Sch name = CRAM_A12 +#set_property PACKAGE_PIN P14 [get_ports {MemAdr[12]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[12]}] +##Bank = 14, Pin name = IO_L18P_T2_A12_D28_14, Sch name = CRAM_A13 +#set_property PACKAGE_PIN U16 [get_ports {MemAdr[13]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[13]}] +##Bank = 14, Pin name = IO_L13N_T2_MRCC_14, Sch name = CRAM_A14 +#set_property PACKAGE_PIN R15 [get_ports {MemAdr[14]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[14]}] +##Bank = 14, Pin name = IO_L8P_T1_D11_14, Sch name = CRAM_A15 +#set_property PACKAGE_PIN N14 [get_ports {MemAdr[15]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[15]}] +##Bank = 14, Pin name = IO_L11N_T1_SRCC_14, Sch name = CRAM_A16 +#set_property PACKAGE_PIN N16 [get_ports {MemAdr[16]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[16]}] +##Bank = 14, Pin name = IO_L6N_T0_D08_VREF_14, Sch name = CRAM_A17 +#set_property PACKAGE_PIN M13 [get_ports {MemAdr[17]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[17]}] +##Bank = 14, Pin name = IO_L18N_T2_A11_D27_14, Sch name = CRAM_A18 +#set_property PACKAGE_PIN V17 [get_ports {MemAdr[18]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[18]}] +##Bank = 14, Pin name = IO_L17P_T2_A14_D30_14, Sch name = CRAM_A19 +#set_property PACKAGE_PIN U17 [get_ports {MemAdr[19]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[19]}] +##Bank = 14, Pin name = IO_L24N_T3_A00_D16_14, Sch name = CRAM_A20 +#set_property PACKAGE_PIN T10 [get_ports {MemAdr[20]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[20]}] +##Bank = 14, Pin name = IO_L10P_T1_D14_14, Sch name = CRAM_A21 +#set_property PACKAGE_PIN M16 [get_ports {MemAdr[21]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[21]}] +##Bank = 14, Pin name = IO_L23N_T3_A02_D18_14, Sch name = CRAM_A22 +#set_property PACKAGE_PIN U13 [get_ports {MemAdr[22]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[22]}] \ No newline at end of file From a94cf440c1122c5803f442d4c4695e899d66c932 Mon Sep 17 00:00:00 2001 From: yannickreiss Date: Tue, 26 Sep 2023 11:34:40 +0200 Subject: [PATCH 06/16] Add constraints for stage 1 --- fpga/constrainits.xdc | 512 +++++++++++++++++++++--------------------- 1 file changed, 256 insertions(+), 256 deletions(-) diff --git a/fpga/constrainits.xdc b/fpga/constrainits.xdc index 632ff73..463edd0 100755 --- a/fpga/constrainits.xdc +++ b/fpga/constrainits.xdc @@ -5,717 +5,717 @@ ## Clock signal ##Bank = 35, Pin name = IO_L12P_T1_MRCC_35, Sch Wname = CLK100MHZ -set_property PACKAGE_PIN E3 [get_ports clk] +set_property PACKAGE_PIN E3 [get_ports clk] set_property IOSTANDARD LVCMOS33 [get_ports clk] create_clock -add -name clk -period 10.00 -waveform {0 5} [get_ports clk] - + ## Switches ##Bank = 34, Pin name = IO_L21P_T3_DQS_34, Sch name = SW0 - set_property PACKAGE_PIN U9 [get_ports {sw[0]}] + set_property PACKAGE_PIN U9 [get_ports {sw[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}] ##Bank = 34, Pin name = IO_25_34, Sch name = SW1 -set_property PACKAGE_PIN U8 [get_ports {sw[1]}] +set_property PACKAGE_PIN U8 [get_ports {sw[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}] ##Bank = 34, Pin name = IO_L23P_T3_34, Sch name = SW2 -set_property PACKAGE_PIN R7 [get_ports {sw[2]}] +set_property PACKAGE_PIN R7 [get_ports {sw[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}] ##Bank = 34, Pin name = IO_L19P_T3_34, Sch name = SW3 -set_property PACKAGE_PIN R6 [get_ports {sw[3]}] +set_property PACKAGE_PIN R6 [get_ports {sw[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}] ##Bank = 34, Pin name = IO_L19N_T3_VREF_34, Sch name = SW4 -set_property PACKAGE_PIN R5 [get_ports {sw[4]}] +set_property PACKAGE_PIN R5 [get_ports {sw[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}] ##Bank = 34, Pin name = IO_L20P_T3_34, Sch name = SW5 -set_property PACKAGE_PIN V7 [get_ports {sw[5]}] +set_property PACKAGE_PIN V7 [get_ports {sw[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}] ##Bank = 34, Pin name = IO_L20N_T3_34, Sch name = SW6 -set_property PACKAGE_PIN V6 [get_ports {sw[6]}] +set_property PACKAGE_PIN V6 [get_ports {sw[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}] ##Bank = 34, Pin name = IO_L10P_T1_34, Sch name = SW7 -set_property PACKAGE_PIN V5 [get_ports {sw[7]}] +set_property PACKAGE_PIN V5 [get_ports {sw[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}] ##Bank = 34, Pin name = IO_L8P_T1-34, Sch name = SW8 -set_property PACKAGE_PIN U4 [get_ports {sw[8]}] - set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}] +#set_property PACKAGE_PIN U4 [get_ports {sw[8]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}] ##Bank = 34, Pin name = IO_L9N_T1_DQS_34, Sch name = SW9 -set_property PACKAGE_PIN V2 [get_ports {sw[9]}] - set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}] +#set_property PACKAGE_PIN V2 [get_ports {sw[9]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}] ##Bank = 34, Pin name = IO_L9P_T1_DQS_34, Sch name = SW10 -set_property PACKAGE_PIN U2 [get_ports {sw[10]}] - set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}] +#set_property PACKAGE_PIN U2 [get_ports {sw[10]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}] ##Bank = 34, Pin name = IO_L11N_T1_MRCC_34, Sch name = SW11 -set_property PACKAGE_PIN T3 [get_ports {sw[11]}] - set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}] +#set_property PACKAGE_PIN T3 [get_ports {sw[11]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}] ##Bank = 34, Pin name = IO_L17N_T2_34, Sch name = SW12 -set_property PACKAGE_PIN T1 [get_ports {sw[12]}] - set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}] +#set_property PACKAGE_PIN T1 [get_ports {sw[12]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}] ##Bank = 34, Pin name = IO_L11P_T1_SRCC_34, Sch name = SW13 -set_property PACKAGE_PIN R3 [get_ports {sw[13]}] - set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}] +#set_property PACKAGE_PIN R3 [get_ports {sw[13]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}] ##Bank = 34, Pin name = IO_L14N_T2_SRCC_34, Sch name = SW14 -set_property PACKAGE_PIN P3 [get_ports {sw[14]}] - set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}] +#set_property PACKAGE_PIN P3 [get_ports {sw[14]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}] ##Bank = 34, Pin name = IO_L14P_T2_SRCC_34, Sch name = SW15 -set_property PACKAGE_PIN P4 [get_ports {sw[15]}] - set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}] - +#set_property PACKAGE_PIN P4 [get_ports {sw[15]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}] + ## LEDs ##Bank = 34, Pin name = IO_L24N_T3_34, Sch name = LED0 -set_property PACKAGE_PIN T8 [get_ports {led[0]}] +set_property PACKAGE_PIN T8 [get_ports {led[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}] #Bank = 34, Pin name = IO_L21N_T3_DQS_34, Sch name = LED1 -set_property PACKAGE_PIN V9 [get_ports {led[1]}] +set_property PACKAGE_PIN V9 [get_ports {led[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}] #Bank = 34, Pin name = IO_L24P_T3_34, Sch name = LED2 - set_property PACKAGE_PIN R8 [get_ports {led[2]}] + set_property PACKAGE_PIN R8 [get_ports {led[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}] #Bank = 34, Pin name = IO_L23N_T3_34, Sch name = LED3 - set_property PACKAGE_PIN T6 [get_ports {led[3]}] + set_property PACKAGE_PIN T6 [get_ports {led[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}] #Bank = 34, Pin name = IO_L12P_T1_MRCC_34, Sch name = LED4 -set_property PACKAGE_PIN T5 [get_ports {led[4]}] +set_property PACKAGE_PIN T5 [get_ports {led[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}] #Bank = 34, Pin name = IO_L12N_T1_MRCC_34, Sch name = LED5 -set_property PACKAGE_PIN T4 [get_ports {led[5]}] +set_property PACKAGE_PIN T4 [get_ports {led[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}] #Bank = 34, Pin name = IO_L22P_T3_34, Sch name = LED6 -set_property PACKAGE_PIN U7 [get_ports {led[6]}] +set_property PACKAGE_PIN U7 [get_ports {led[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}] #Bank = 34, Pin name = IO_L22N_T3_34, Sch name = LED7 -set_property PACKAGE_PIN U6 [get_ports {led[7]}] +set_property PACKAGE_PIN U6 [get_ports {led[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}] ##Bank = 34, Pin name = IO_L10N_T1_34, Sch name = LED8 -set_property PACKAGE_PIN V4 [get_ports {led[8]}] - set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}] +#set_property PACKAGE_PIN V4 [get_ports {led[8]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}] ##Bank = 34, Pin name = IO_L8N_T1_34, Sch name = LED9 -set_property PACKAGE_PIN U3 [get_ports {led[9]}] - set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}] +#set_property PACKAGE_PIN U3 [get_ports {led[9]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}] ##Bank = 34, Pin name = IO_L7N_T1_34, Sch name = LED10 -set_property PACKAGE_PIN V1 [get_ports {led[10]}] - set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}] +#set_property PACKAGE_PIN V1 [get_ports {led[10]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}] ##Bank = 34, Pin name = IO_L17P_T2_34, Sch name = LED11 -set_property PACKAGE_PIN R1 [get_ports {led[11]}] - set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}] +#set_property PACKAGE_PIN R1 [get_ports {led[11]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}] ##Bank = 34, Pin name = IO_L13N_T2_MRCC_34, Sch name = LED12 -set_property PACKAGE_PIN P5 [get_ports {led[12]}] - set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}] +#set_property PACKAGE_PIN P5 [get_ports {led[12]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}] ##Bank = 34, Pin name = IO_L7P_T1_34, Sch name = LED13 -set_property PACKAGE_PIN U1 [get_ports {led[13]}] - set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}] +#set_property PACKAGE_PIN U1 [get_ports {led[13]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}] ##Bank = 34, Pin name = IO_L15N_T2_DQS_34, Sch name = LED14 -set_property PACKAGE_PIN R2 [get_ports {led[14]}] - set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}] +#set_property PACKAGE_PIN R2 [get_ports {led[14]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}] ##Bank = 34, Pin name = IO_L15P_T2_DQS_34, Sch name = LED15 -set_property PACKAGE_PIN P2 [get_ports {led[15]}] - set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}] +#set_property PACKAGE_PIN P2 [get_ports {led[15]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}] ##Bank = 34, Pin name = IO_L5P_T0_34, Sch name = LED16_R -set_property PACKAGE_PIN K5 [get_ports {rgb[0]}] - set_property IOSTANDARD LVCMOS33 [get_ports {rgb[0]}] +#set_property PACKAGE_PIN K5 [get_ports {rgb[0]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {rgb[0]}] ##Bank = 15, Pin name = IO_L5P_T0_AD9P_15, Sch name = LED16_G -set_property PACKAGE_PIN F13 [get_ports {rgb[1]}] - set_property IOSTANDARD LVCMOS33 [get_ports {rgb[1]}] +#set_property PACKAGE_PIN F13 [get_ports {rgb[1]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {rgb[1]}] ##Bank = 35, Pin name = IO_L19N_T3_VREF_35, Sch name = LED16_B -set_property PACKAGE_PIN F6 [get_ports {rgb[2]}] - set_property IOSTANDARD LVCMOS33 [get_ports {rgb[2]}] +#set_property PACKAGE_PIN F6 [get_ports {rgb[2]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {rgb[2]}] ##Bank = 34, Pin name = IO_0_34, Sch name = LED17_R -set_property PACKAGE_PIN K6 [get_ports {rgb[3]}] - set_property IOSTANDARD LVCMOS33 [get_ports {rgb[3]}] +#set_property PACKAGE_PIN K6 [get_ports {rgb[3]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {rgb[3]}] ##Bank = 35, Pin name = IO_24P_T3_35, Sch name = LED17_G -set_property PACKAGE_PIN H6 [get_ports {rgb[4]}] - set_property IOSTANDARD LVCMOS33 [get_ports {rgb[4]}] +#set_property PACKAGE_PIN H6 [get_ports {rgb[4]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {rgb[4]}] ##Bank = CONFIG, Pin name = IO_L3N_T0_DQS_EMCCLK_14, Sch name = LED17_B -set_property PACKAGE_PIN L16 [get_ports {rgb[5]}] - set_property IOSTANDARD LVCMOS33 [get_ports {rgb[5]}] +#set_property PACKAGE_PIN L16 [get_ports {rgb[5]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {rgb[5]}] ##7 segment display ##Bank = 34, Pin name = IO_L2N_T0_34, Sch name = CA -#set_property PACKAGE_PIN L3 [get_ports {seg[0]}] +#set_property PACKAGE_PIN L3 [get_ports {seg[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}] ##Bank = 34, Pin name = IO_L3N_T0_DQS_34, Sch name = CB -#set_property PACKAGE_PIN N1 [get_ports {seg[1]}] +#set_property PACKAGE_PIN N1 [get_ports {seg[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}] ##Bank = 34, Pin name = IO_L6N_T0_VREF_34, Sch name = CC -#set_property PACKAGE_PIN L5 [get_ports {seg[2]}] +#set_property PACKAGE_PIN L5 [get_ports {seg[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}] ##Bank = 34, Pin name = IO_L5N_T0_34, Sch name = CD -#set_property PACKAGE_PIN L4 [get_ports {seg[3]}] +#set_property PACKAGE_PIN L4 [get_ports {seg[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}] ##Bank = 34, Pin name = IO_L2P_T0_34, Sch name = CE -#set_property PACKAGE_PIN K3 [get_ports {seg[4]}] +#set_property PACKAGE_PIN K3 [get_ports {seg[4]}] #set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}] ##Bank = 34, Pin name = IO_L4N_T0_34, Sch name = CF -#set_property PACKAGE_PIN M2 [get_ports {seg[5]}] +#set_property PACKAGE_PIN M2 [get_ports {seg[5]}] #set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}] ##Bank = 34, Pin name = IO_L6P_T0_34, Sch name = CG -#set_property PACKAGE_PIN L6 [get_ports {seg[6]}] +#set_property PACKAGE_PIN L6 [get_ports {seg[6]}] #set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}] ##Bank = 34, Pin name = IO_L16P_T2_34, Sch name = DP -#set_property PACKAGE_PIN M4 [get_ports dp] +#set_property PACKAGE_PIN M4 [get_ports dp] #set_property IOSTANDARD LVCMOS33 [get_ports dp] ##Bank = 34, Pin name = IO_L18N_T2_34, Sch name = AN0 -#set_property PACKAGE_PIN N6 [get_ports {an[0]}] +#set_property PACKAGE_PIN N6 [get_ports {an[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}] ##Bank = 34, Pin name = IO_L18P_T2_34, Sch name = AN1 -#set_property PACKAGE_PIN M6 [get_ports {an[1]}] +#set_property PACKAGE_PIN M6 [get_ports {an[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}] ##Bank = 34, Pin name = IO_L4P_T0_34, Sch name = AN2 -#set_property PACKAGE_PIN M3 [get_ports {an[2]}] +#set_property PACKAGE_PIN M3 [get_ports {an[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}] ##Bank = 34, Pin name = IO_L13_T2_MRCC_34, Sch name = AN3 -#set_property PACKAGE_PIN N5 [get_ports {an[3]}] +#set_property PACKAGE_PIN N5 [get_ports {an[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}] ##Bank = 34, Pin name = IO_L3P_T0_DQS_34, Sch name = AN4 -#set_property PACKAGE_PIN N2 [get_ports {an[4]}] +#set_property PACKAGE_PIN N2 [get_ports {an[4]}] #set_property IOSTANDARD LVCMOS33 [get_ports {an[4]}] ##Bank = 34, Pin name = IO_L16N_T2_34, Sch name = AN5 -#set_property PACKAGE_PIN N4 [get_ports {an[5]}] +#set_property PACKAGE_PIN N4 [get_ports {an[5]}] #set_property IOSTANDARD LVCMOS33 [get_ports {an[5]}] -##Bank = 34, Pin name = IO_L1P_T0_34, Sch name = AN6 -#set_property PACKAGE_PIN L1 [get_ports {an[6]}] +##Bank = 34, Pin name = IO_L1P_T0_34, Sch name = ANyte_out6 +#set_property PACKAGE_PIN L1 [get_ports {an[6]}] #set_property IOSTANDARD LVCMOS33 [get_ports {an[6]}] ##Bank = 34, Pin name = IO_L1N_T034, Sch name = AN7 -#set_property PACKAGE_PIN M1 [get_ports {an[7]}] +#set_property PACKAGE_PIN M1 [get_ports {an[7]}] #set_property IOSTANDARD LVCMOS33 [get_ports {an[7]}] ##Buttons ##Bank = 15, Pin name = IO_L3P_T0_DQS_AD1P_15, Sch name = CPU_RESET -set_property PACKAGE_PIN C12 [get_ports reset] - set_property IOSTANDARD LVCMOS33 [get_ports reset] +#set_property PACKAGE_PIN C12 [get_ports reset] +# set_property IOSTANDARD LVCMOS33 [get_ports reset] ##Bank = 15, Pin name = IO_L11N_T1_SRCC_15, Sch name = BTNC -#set_property PACKAGE_PIN E16 [get_ports clk] +#set_property PACKAGE_PIN E16 [get_ports clk] # set_property IOSTANDARD LVCMOS33 [get_ports clk] ##Bank = 15, Pin name = IO_L14P_T2_SRCC_15, Sch name = BTNU -#set_property PACKAGE_PIN F15 [get_ports btnU] +#set_property PACKAGE_PIN F15 [get_ports btnU] #set_property IOSTANDARD LVCMOS33 [get_ports btnU] ##Bank = CONFIG, Pin name = IO_L15N_T2_DQS_DOUT_CSO_B_14, Sch name = BTNL -#set_property PACKAGE_PIN T16 [get_ports btnL] +#set_property PACKAGE_PIN T16 [get_ports btnL] #set_property IOSTANDARD LVCMOS33 [get_ports btnL] ##Bank = 14, Pin name = IO_25_14, Sch name = BTNR -#set_property PACKAGE_PIN R10 [get_ports btnR] +#set_property PACKAGE_PIN R10 [get_ports btnR] #set_property IOSTANDARD LVCMOS33 [get_ports btnR] ##Bank = 14, Pin name = IO_L21P_T3_DQS_14, Sch name = BTND -#set_property PACKAGE_PIN V10 [get_ports btnD] +#set_property PACKAGE_PIN V10 [get_ports btnD] #set_property IOSTANDARD LVCMOS33 [get_ports btnD] - + ##Pmod Header JA ##Bank = 15, Pin name = IO_L1N_T0_AD0N_15, Sch name = JA1 -#set_property PACKAGE_PIN B13 [get_ports {JA[0]}] +#set_property PACKAGE_PIN B13 [get_ports {JA[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}] ##Bank = 15, Pin name = IO_L5N_T0_AD9N_15, Sch name = JA2 -#set_property PACKAGE_PIN F14 [get_ports {JA[1]}] +#set_property PACKAGE_PIN F14 [get_ports {JA[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}] ##Bank = 15, Pin name = IO_L16N_T2_A27_15, Sch name = JA3 -#set_property PACKAGE_PIN D17 [get_ports {JA[2]}] +#set_property PACKAGE_PIN D17 [get_ports {JA[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}] ##Bank = 15, Pin name = IO_L16P_T2_A28_15, Sch name = JA4 -#set_property PACKAGE_PIN E17 [get_ports {JA[3]}] +#set_property PACKAGE_PIN E17 [get_ports {JA[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}] ##Bank = 15, Pin name = IO_0_15, Sch name = JA7 -#set_property PACKAGE_PIN G13 [get_ports {JA[4]}] +#set_property PACKAGE_PIN G13 [get_ports {JA[4]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}] ##Bank = 15, Pin name = IO_L20N_T3_A19_15, Sch name = JA8 -#set_property PACKAGE_PIN C17 [get_ports {JA[5]}] +#set_property PACKAGE_PIN C17 [get_ports {JA[5]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}] ##Bank = 15, Pin name = IO_L21N_T3_A17_15, Sch name = JA9 -#set_property PACKAGE_PIN D18 [get_ports {JA[6]}] +#set_property PACKAGE_PIN D18 [get_ports {JA[6]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}] ##Bank = 15, Pin name = IO_L21P_T3_DQS_15, Sch name = JA10 -#set_property PACKAGE_PIN E18 [get_ports {JA[7]}] +#set_property PACKAGE_PIN E18 [get_ports {JA[7]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}] ##Pmod Header JB ##Bank = 15, Pin name = IO_L15N_T2_DQS_ADV_B_15, Sch name = JB1 -#set_property PACKAGE_PIN G14 [get_ports {JB[0]}] +#set_property PACKAGE_PIN G14 [get_ports {JB[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}] ##Bank = 14, Pin name = IO_L13P_T2_MRCC_14, Sch name = JB2 -#set_property PACKAGE_PIN P15 [get_ports {JB[1]}] +#set_property PACKAGE_PIN P15 [get_ports {JB[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}] ##Bank = 14, Pin name = IO_L21N_T3_DQS_A06_D22_14, Sch name = JB3 -#set_property PACKAGE_PIN V11 [get_ports {JB[2]}] +#set_property PACKAGE_PIN V11 [get_ports {JB[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}] ##Bank = CONFIG, Pin name = IO_L16P_T2_CSI_B_14, Sch name = JB4 -#set_property PACKAGE_PIN V15 [get_ports {JB[3]}] +#set_property PACKAGE_PIN V15 [get_ports {JB[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}] ##Bank = 15, Pin name = IO_25_15, Sch name = JB7 -#set_property PACKAGE_PIN K16 [get_ports {JB[4]}] +#set_property PACKAGE_PIN K16 [get_ports {JB[4]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}] ##Bank = CONFIG, Pin name = IO_L15P_T2_DQS_RWR_B_14, Sch name = JB8 -#set_property PACKAGE_PIN R16 [get_ports {JB[5]}] +#set_property PACKAGE_PIN R16 [get_ports {JB[5]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}] ##Bank = 14, Pin name = IO_L24P_T3_A01_D17_14, Sch name = JB9 -#set_property PACKAGE_PIN T9 [get_ports {JB[6]}] +#set_property PACKAGE_PIN T9 [get_ports {JB[6]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}] -##Bank = 14, Pin name = IO_L19N_T3_A09_D25_VREF_14, Sch name = JB10 -#set_property PACKAGE_PIN U11 [get_ports {JB[7]}] +##Bank = 14, Pin name = IO_L19N_T3_A09_D25_VREF_14, Sch name = JB10 +#set_property PACKAGE_PIN U11 [get_ports {JB[7]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}] - + ##Pmod Header JC ##Bank = 35, Pin name = IO_L23P_T3_35, Sch name = JC1 -#set_property PACKAGE_PIN K2 [get_ports {JC[0]}] +#set_property PACKAGE_PIN K2 [get_ports {JC[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}] ##Bank = 35, Pin name = IO_L6P_T0_35, Sch name = JC2 -#set_property PACKAGE_PIN E7 [get_ports {JC[1]}] +#set_property PACKAGE_PIN E7 [get_ports {JC[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}] ##Bank = 35, Pin name = IO_L22P_T3_35, Sch name = JC3 -#set_property PACKAGE_PIN J3 [get_ports {JC[2]}] +#set_property PACKAGE_PIN J3 [get_ports {JC[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}] ##Bank = 35, Pin name = IO_L21P_T3_DQS_35, Sch name = JC4 -#set_property PACKAGE_PIN J4 [get_ports {JC[3]}] +#set_property PACKAGE_PIN J4 [get_ports {JC[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}] ##Bank = 35, Pin name = IO_L23N_T3_35, Sch name = JC7 -#set_property PACKAGE_PIN K1 [get_ports {JC[4]}] +#set_property PACKAGE_PIN K1 [get_ports {JC[4]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}] ##Bank = 35, Pin name = IO_L5P_T0_AD13P_35, Sch name = JC8 -#set_property PACKAGE_PIN E6 [get_ports {JC[5]}] +#set_property PACKAGE_PIN E6 [get_ports {JC[5]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}] ##Bank = 35, Pin name = IO_L22N_T3_35, Sch name = JC9 -#set_property PACKAGE_PIN J2 [get_ports {JC[6]}] +#set_property PACKAGE_PIN J2 [get_ports {JC[6]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}] ##Bank = 35, Pin name = IO_L19P_T3_35, Sch name = JC10 -#set_property PACKAGE_PIN G6 [get_ports {JC[7]}] +#set_property PACKAGE_PIN G6 [get_ports {JC[7]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}] - - + + ##Pmod Header JD ##Bank = 35, Pin name = IO_L21N_T2_DQS_35, Sch name = JD1 -#set_property PACKAGE_PIN H4 [get_ports {JD[0]}] +#set_property PACKAGE_PIN H4 [get_ports {JD[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JD[0]}] ##Bank = 35, Pin name = IO_L17P_T2_35, Sch name = JD2 -#set_property PACKAGE_PIN H1 [get_ports {JD[1]}] +#set_property PACKAGE_PIN H1 [get_ports {JD[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JD[1]}] ##Bank = 35, Pin name = IO_L17N_T2_35, Sch name = JD3 -#set_property PACKAGE_PIN G1 [get_ports {JD[2]}] +#set_property PACKAGE_PIN G1 [get_ports {JD[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JD[2]}] ##Bank = 35, Pin name = IO_L20N_T3_35, Sch name = JD4 -#set_property PACKAGE_PIN G3 [get_ports {JD[3]}] +#set_property PACKAGE_PIN G3 [get_ports {JD[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JD[3]}] ##Bank = 35, Pin name = IO_L15P_T2_DQS_35, Sch name = JD7 -#set_property PACKAGE_PIN H2 [get_ports {JD[4]}] +#set_property PACKAGE_PIN H2 [get_ports {JD[4]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JD[4]}] ##Bank = 35, Pin name = IO_L20P_T3_35, Sch name = JD8 -#set_property PACKAGE_PIN G4 [get_ports {JD[5]}] +#set_property PACKAGE_PIN G4 [get_ports {JD[5]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JD[5]}] ##Bank = 35, Pin name = IO_L15N_T2_DQS_35, Sch name = JD9 -#set_property PACKAGE_PIN G2 [get_ports {JD[6]}] +#set_property PACKAGE_PIN G2 [get_ports {JD[6]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JD[6]}] ##Bank = 35, Pin name = IO_L13N_T2_MRCC_35, Sch name = JD10 -#set_property PACKAGE_PIN F3 [get_ports {JD[7]}] +#set_property PACKAGE_PIN F3 [get_ports {JD[7]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JD[7]}] - + ##Pmod Header JXADC ##Bank = 15, Pin name = IO_L9P_T1_DQS_AD3P_15, Sch name = XADC1_P -> XA1_P -#set_property PACKAGE_PIN A13 [get_ports {JXADC[0]}] +#set_property PACKAGE_PIN A13 [get_ports {JXADC[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}] ##Bank = 15, Pin name = IO_L8P_T1_AD10P_15, Sch name = XADC2_P -> XA2_P -#set_property PACKAGE_PIN A15 [get_ports {JXADC[1]}] +#set_property PACKAGE_PIN A15 [get_ports {JXADC[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}] ##Bank = 15, Pin name = IO_L7P_T1_AD2P_15, Sch name = XADC3_P -> XA3_P -#set_property PACKAGE_PIN B16 [get_ports {JXADC[2]}] +#set_property PACKAGE_PIN B16 [get_ports {JXADC[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}] ##Bank = 15, Pin name = IO_L10P_T1_AD11P_15, Sch name = XADC4_P -> XA4_P -#set_property PACKAGE_PIN B18 [get_ports {JXADC[3]}] +#set_property PACKAGE_PIN B18 [get_ports {JXADC[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}] ##Bank = 15, Pin name = IO_L9N_T1_DQS_AD3N_15, Sch name = XADC1_N -> XA1_N -#set_property PACKAGE_PIN A14 [get_ports {JXADC[4]}] +#set_property PACKAGE_PIN A14 [get_ports {JXADC[4]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}] ##Bank = 15, Pin name = IO_L8N_T1_AD10N_15, Sch name = XADC2_N -> XA2_N -#set_property PACKAGE_PIN A16 [get_ports {JXADC[5]}] +#set_property PACKAGE_PIN A16 [get_ports {JXADC[5]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}] -##Bank = 15, Pin name = IO_L7N_T1_AD2N_15, Sch name = XADC3_N -> XA3_N -#set_property PACKAGE_PIN B17 [get_ports {JXADC[6]}] +##Bank = 15, Pin name = IO_L7N_T1_AD2N_15, Sch name = XADC3_N -> XA3_N +#set_property PACKAGE_PIN B17 [get_ports {JXADC[6]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}] ##Bank = 15, Pin name = IO_L10N_T1_AD11N_15, Sch name = XADC4_N -> XA4_N -#set_property PACKAGE_PIN A18 [get_ports {JXADC[7]}] +#set_property PACKAGE_PIN A18 [get_ports {JXADC[7]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}] ##VGA Connector ##Bank = 35, Pin name = IO_L8N_T1_AD14N_35, Sch name = VGA_R0 -set_property PACKAGE_PIN A3 [get_ports {vgaRed[0]}] - set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}] +#set_property PACKAGE_PIN A3 [get_ports {vgaRed[0]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}] ##Bank = 35, Pin name = IO_L7N_T1_AD6N_35, Sch name = VGA_R1 -set_property PACKAGE_PIN B4 [get_ports {vgaRed[1]}] - set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}] +#set_property PACKAGE_PIN B4 [get_ports {vgaRed[1]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}] ##Bank = 35, Pin name = IO_L1N_T0_AD4N_35, Sch name = VGA_R2 -set_property PACKAGE_PIN C5 [get_ports {vgaRed[2]}] - set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}] +#set_property PACKAGE_PIN C5 [get_ports {vgaRed[2]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}] ##Bank = 35, Pin name = IO_L8P_T1_AD14P_35, Sch name = VGA_R3 -#set_property PACKAGE_PIN A4 [get_ports {vgaRed[3]}] +#set_property PACKAGE_PIN A4 [get_ports {vgaRed[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}] ##Bank = 35, Pin name = IO_L2P_T0_AD12P_35, Sch name = VGA_B0 -set_property PACKAGE_PIN B7 [get_ports {vgaBlue[0]}] - set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}] +#set_property PACKAGE_PIN B7 [get_ports {vgaBlue[0]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}] ##Bank = 35, Pin name = IO_L4N_T0_35, Sch name = VGA_B1 -set_property PACKAGE_PIN C7 [get_ports {vgaBlue[1]}] - set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}] +#set_property PACKAGE_PIN C7 [get_ports {vgaBlue[1]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}] ##Bank = 35, Pin name = IO_L6N_T0_VREF_35, Sch name = VGA_B2 -set_property PACKAGE_PIN D7 [get_ports {vgaBlue[2]}] - set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}] +#set_property PACKAGE_PIN D7 [get_ports {vgaBlue[2]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}] ##Bank = 35, Pin name = IO_L4P_T0_35, Sch name = VGA_B3 -#set_property PACKAGE_PIN D8 [get_ports {vgaBlue[3]}] +#set_property PACKAGE_PIN D8 [get_ports {vgaBlue[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}] ##Bank = 35, Pin name = IO_L1P_T0_AD4P_35, Sch name = VGA_G0 -set_property PACKAGE_PIN C6 [get_ports {vgaGreen[0]}] - set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}] +#set_property PACKAGE_PIN C6 [get_ports {vgaGreen[0]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}] ##Bank = 35, Pin name = IO_L3N_T0_DQS_AD5N_35, Sch name = VGA_G1 -set_property PACKAGE_PIN A5 [get_ports {vgaGreen[1]}] - set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}] +#set_property PACKAGE_PIN A5 [get_ports {vgaGreen[1]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}] ##Bank = 35, Pin name = IO_L2N_T0_AD12N_35, Sch name = VGA_G2 -#set_property PACKAGE_PIN B6 [get_ports {vgaGreen[2]}] +#set_property PACKAGE_PIN B6 [get_ports {vgaGreen[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}] ##Bank = 35, Pin name = IO_L3P_T0_DQS_AD5P_35, Sch name = VGA_G3 -#set_property PACKAGE_PIN A6 [get_ports {vgaGreen[3]}] +#set_property PACKAGE_PIN A6 [get_ports {vgaGreen[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}] ##Bank = 15, Pin name = IO_L4P_T0_15, Sch name = VGA_HS -set_property PACKAGE_PIN B11 [get_ports Hsync] - set_property IOSTANDARD LVCMOS33 [get_ports Hsync] +#set_property PACKAGE_PIN B11 [get_ports Hsync] +# set_property IOSTANDARD LVCMOS33 [get_ports Hsync] ##Bank = 15, Pin name = IO_L3N_T0_DQS_AD1N_15, Sch name = VGA_VS -set_property PACKAGE_PIN B12 [get_ports Vsync] - set_property IOSTANDARD LVCMOS33 [get_ports Vsync] +#set_property PACKAGE_PIN B12 [get_ports Vsync] +# set_property IOSTANDARD LVCMOS33 [get_ports Vsync] ##Micro SD Connector ##Bank = 35, Pin name = IO_L14P_T2_SRCC_35, Sch name = SD_RESET -#set_property PACKAGE_PIN E2 [get_ports sdReset] +#set_property PACKAGE_PIN E2 [get_ports sdReset] #set_property IOSTANDARD LVCMOS33 [get_ports sdReset] ##Bank = 35, Pin name = IO_L9N_T1_DQS_AD7N_35, Sch name = SD_CD -#set_property PACKAGE_PIN A1 [get_ports sdCD] +#set_property PACKAGE_PIN A1 [get_ports sdCD] #set_property IOSTANDARD LVCMOS33 [get_ports sdCD] ##Bank = 35, Pin name = IO_L9P_T1_DQS_AD7P_35, Sch name = SD_SCK -#set_property PACKAGE_PIN B1 [get_ports sdSCK] +#set_property PACKAGE_PIN B1 [get_ports sdSCK] #set_property IOSTANDARD LVCMOS33 [get_ports sdSCK] ##Bank = 35, Pin name = IO_L16N_T2_35, Sch name = SD_CMD -#set_property PACKAGE_PIN C1 [get_ports sdCmd] +#set_property PACKAGE_PIN C1 [get_ports sdCmd] #set_property IOSTANDARD LVCMOS33 [get_ports sdCmd] ##Bank = 35, Pin name = IO_L16P_T2_35, Sch name = SD_DAT0 -#set_property PACKAGE_PIN C2 [get_ports {sdData[0]}] +#set_property PACKAGE_PIN C2 [get_ports {sdData[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {sdData[0]}] ##Bank = 35, Pin name = IO_L18N_T2_35, Sch name = SD_DAT1 -#set_property PACKAGE_PIN E1 [get_ports {sdData[1]}] +#set_property PACKAGE_PIN E1 [get_ports {sdData[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {sdData[1]}] ##Bank = 35, Pin name = IO_L18P_T2_35, Sch name = SD_DAT2 -#set_property PACKAGE_PIN F1 [get_ports {sdData[2]}] +#set_property PACKAGE_PIN F1 [get_ports {sdData[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {sdData[2]}] ##Bank = 35, Pin name = IO_L14N_T2_SRCC_35, Sch name = SD_DAT3 -#set_property PACKAGE_PIN D2 [get_ports {sdData[3]}] +#set_property PACKAGE_PIN D2 [get_ports {sdData[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {sdData[3]}] ##Accelerometer ##Bank = 15, Pin name = IO_L6N_T0_VREF_15, Sch name = ACL_MISO -#set_property PACKAGE_PIN D13 [get_ports MISO] +#set_property PACKAGE_PIN D13 [get_ports MISO] # set_property IOSTANDARD LVCMOS33 [get_ports MISO] #Bank = 15, Pin name = IO_L2N_T0_AD8N_15, Sch name = ACL_MOSI -#set_property PACKAGE_PIN B14 [get_ports MOSI] +#set_property PACKAGE_PIN B14 [get_ports MOSI] # set_property IOSTANDARD LVCMOS33 [get_ports MOSI] #Bank = 15, Pin name = IO_L12P_T1_MRCC_15, Sch name = ACL_SCLK -#set_property PACKAGE_PIN D15 [get_ports SCLK] +#set_property PACKAGE_PIN D15 [get_ports SCLK] # set_property IOSTANDARD LVCMOS33 [get_ports SCLK] #Bank = 15, Pin name = IO_L12N_T1_MRCC_15, Sch name = ACL_CSN -#set_property PACKAGE_PIN C15 [get_ports SS] +#set_property PACKAGE_PIN C15 [get_ports SS] # set_property IOSTANDARD LVCMOS33 [get_ports SS] ##Bank = 15, Pin name = IO_L20P_T3_A20_15, Sch name = ACL_INT1 -#set_property PACKAGE_PIN C16 [get_ports aclInt1] +#set_property PACKAGE_PIN C16 [get_ports aclInt1] #set_property IOSTANDARD LVCMOS33 [get_ports aclInt1] ##Bank = 15, Pin name = IO_L11P_T1_SRCC_15, Sch name = ACL_INT2 -#set_property PACKAGE_PIN E15 [get_ports aclInt2] +#set_property PACKAGE_PIN E15 [get_ports aclInt2] #set_property IOSTANDARD LVCMOS33 [get_ports aclInt2] ##Temperature Sensor ##Bank = 15, Pin name = IO_L14N_T2_SRCC_15, Sch name = TMP_SCL -#set_property PACKAGE_PIN F16 [get_ports tmpSCL] +#set_property PACKAGE_PIN F16 [get_ports tmpSCL] #set_property IOSTANDARD LVCMOS33 [get_ports tmpSCL] ##Bank = 15, Pin name = IO_L13N_T2_MRCC_15, Sch name = TMP_SDA -#set_property PACKAGE_PIN G16 [get_ports tmpSDA] +#set_property PACKAGE_PIN G16 [get_ports tmpSDA] #set_property IOSTANDARD LVCMOS33 [get_ports tmpSDA] ##Bank = 15, Pin name = IO_L1P_T0_AD0P_15, Sch name = TMP_INT -#set_property PACKAGE_PIN D14 [get_ports tmpInt] +#set_property PACKAGE_PIN D14 [get_ports tmpInt] #set_property IOSTANDARD LVCMOS33 [get_ports tmpInt] ##Bank = 15, Pin name = IO_L1N_T0_AD0N_15, Sch name = TMP_CT -#set_property PACKAGE_PIN C14 [get_ports tmpCT] +#set_property PACKAGE_PIN C14 [get_ports tmpCT] #set_property IOSTANDARD LVCMOS33 [get_ports tmpCT] ##Omnidirectional Microphone ##Bank = 35, Pin name = IO_25_35, Sch name = M_CLK -#set_property PACKAGE_PIN J5 [get_ports micClk] +#set_property PACKAGE_PIN J5 [get_ports micClk] #set_property IOSTANDARD LVCMOS33 [get_ports micClk] ##Bank = 35, Pin name = IO_L24N_T3_35, Sch name = M_DATA -#set_property PACKAGE_PIN H5 [get_ports micData] +#set_property PACKAGE_PIN H5 [get_ports micData] #set_property IOSTANDARD LVCMOS33 [get_ports micData] ##Bank = 35, Pin name = IO_0_35, Sch name = M_LRSEL -#set_property PACKAGE_PIN F5 [get_ports micLRSel] +#set_property PACKAGE_PIN F5 [get_ports micLRSel] #set_property IOSTANDARD LVCMOS33 [get_ports micLRSel] ##PWM Audio Amplifier ##Bank = 15, Pin name = IO_L4N_T0_15, Sch name = AUD_PWM -#set_property PACKAGE_PIN A11 [get_ports ampPWM] +#set_property PACKAGE_PIN A11 [get_ports ampPWM] #set_property IOSTANDARD LVCMOS33 [get_ports ampPWM] ##Bank = 15, Pin name = IO_L6P_T0_15, Sch name = AUD_SD -#set_property PACKAGE_PIN D12 [get_ports ampSD] +#set_property PACKAGE_PIN D12 [get_ports ampSD] #set_property IOSTANDARD LVCMOS33 [get_ports ampSD] ##USB-RS232 Interface ##Bank = 35, Pin name = IO_L7P_T1_AD6P_35, Sch name = UART_TXD_IN -#set_property PACKAGE_PIN C4 [get_ports RsRx] +#set_property PACKAGE_PIN C4 [get_ports RsRx] #set_property IOSTANDARD LVCMOS33 [get_ports RsRx] ##Bank = 35, Pin name = IO_L11N_T1_SRCC_35, Sch name = UART_RXD_OUT -#set_property PACKAGE_PIN D4 [get_ports RsTx] +#set_property PACKAGE_PIN D4 [get_ports RsTx] #set_property IOSTANDARD LVCMOS33 [get_ports RsTx] ##Bank = 35, Pin name = IO_L12N_T1_MRCC_35, Sch name = UART_CTS -#set_property PACKAGE_PIN D3 [get_ports RsCts] +#set_property PACKAGE_PIN D3 [get_ports RsCts] #set_property IOSTANDARD LVCMOS33 [get_ports RsCts] ##Bank = 35, Pin name = IO_L5N_T0_AD13N_35, Sch name = UART_RTS -#set_property PACKAGE_PIN E5 [get_ports RsRts] +#set_property PACKAGE_PIN E5 [get_ports RsRts] #set_property IOSTANDARD LVCMOS33 [get_ports RsRts] ##USB HID (PS/2) ##Bank = 35, Pin name = IO_L13P_T2_MRCC_35, Sch name = PS2_CLK -#set_property PACKAGE_PIN F4 [get_ports PS2Clk] +#set_property PACKAGE_PIN F4 [get_ports PS2Clk] #set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk] #set_property PULLUP true [get_ports PS2Clk] ##Bank = 35, Pin name = IO_L10N_T1_AD15N_35, Sch name = PS2_DATA -#set_property PACKAGE_PIN B2 [get_ports PS2Data] - #set_property IOSTANDARD LVCMOS33 [get_ports PS2Data] +#set_property PACKAGE_PIN B2 [get_ports PS2Data] + #set_property IOSTANDARD LVCMOS33 [get_ports PS2Data] #set_property PULLUP true [get_ports PS2Data] ##SMSC Ethernet PHY ##Bank = 16, Pin name = IO_L11P_T1_SRCC_16, Sch name = ETH_MDC -#set_property PACKAGE_PIN C9 [get_ports PhyMdc] +#set_property PACKAGE_PIN C9 [get_ports PhyMdc] #set_property IOSTANDARD LVCMOS33 [get_ports PhyMdc] ##Bank = 16, Pin name = IO_L14N_T2_SRCC_16, Sch name = ETH_MDIO -#set_property PACKAGE_PIN A9 [get_ports PhyMdio] +#set_property PACKAGE_PIN A9 [get_ports PhyMdio] #set_property IOSTANDARD LVCMOS33 [get_ports PhyMdio] ##Bank = 35, Pin name = IO_L10P_T1_AD15P_35, Sch name = ETH_RSTN -#set_property PACKAGE_PIN B3 [get_ports PhyRstn] +#set_property PACKAGE_PIN B3 [get_ports PhyRstn] #set_property IOSTANDARD LVCMOS33 [get_ports PhyRstn] ##Bank = 16, Pin name = IO_L6N_T0_VREF_16, Sch name = ETH_CRSDV -#set_property PACKAGE_PIN D9 [get_ports PhyCrs] +#set_property PACKAGE_PIN D9 [get_ports PhyCrs] #set_property IOSTANDARD LVCMOS33 [get_ports PhyCrs] ##Bank = 16, Pin name = IO_L13N_T2_MRCC_16, Sch name = ETH_RXERR -#set_property PACKAGE_PIN C10 [get_ports PhyRxErr] +#set_property PACKAGE_PIN C10 [get_ports PhyRxErr] #set_property IOSTANDARD LVCMOS33 [get_ports PhyRxErr] ##Bank = 16, Pin name = IO_L19N_T3_VREF_16, Sch name = ETH_RXD0 -#set_property PACKAGE_PIN D10 [get_ports {PhyRxd[0]}] +#set_property PACKAGE_PIN D10 [get_ports {PhyRxd[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {PhyRxd[0]}] ##Bank = 16, Pin name = IO_L13P_T2_MRCC_16, Sch name = ETH_RXD1 -#set_property PACKAGE_PIN C11 [get_ports {PhyRxd[1]}] +#set_property PACKAGE_PIN C11 [get_ports {PhyRxd[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {PhyRxd[1]}] ##Bank = 16, Pin name = IO_L11N_T1_SRCC_16, Sch name = ETH_TXEN -#set_property PACKAGE_PIN B9 [get_ports PhyTxEn] +#set_property PACKAGE_PIN B9 [get_ports PhyTxEn] #set_property IOSTANDARD LVCMOS33 [get_ports PhyTxEn] ##Bank = 16, Pin name = IO_L14P_T2_SRCC_16, Sch name = ETH_TXD0 -#set_property PACKAGE_PIN A10 [get_ports {PhyTxd[0]}] +#set_property PACKAGE_PIN A10 [get_ports {PhyTxd[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {PhyTxd[0]}] ##Bank = 16, Pin name = IO_L12N_T1_MRCC_16, Sch name = ETH_TXD1 -#set_property PACKAGE_PIN A8 [get_ports {PhyTxd[1]}] +#set_property PACKAGE_PIN A8 [get_ports {PhyTxd[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {PhyTxd[1]}] ##Bank = 35, Pin name = IO_L11P_T1_SRCC_35, Sch name = ETH_REFCLK -#set_property PACKAGE_PIN D5 [get_ports PhyClk50Mhz] +#set_property PACKAGE_PIN D5 [get_ports PhyClk50Mhz] #set_property IOSTANDARD LVCMOS33 [get_ports PhyClk50Mhz] ##Bank = 16, Pin name = IO_L12P_T1_MRCC_16, Sch name = ETH_INTN -#set_property PACKAGE_PIN B8 [get_ports PhyIntn] +#set_property PACKAGE_PIN B8 [get_ports PhyIntn] #set_property IOSTANDARD LVCMOS33 [get_ports PhyIntn] ##Quad SPI Flash ##Bank = CONFIG, Pin name = CCLK_0, Sch name = QSPI_SCK -#set_property PACKAGE_PIN E9 [get_ports {QspiSCK}] +#set_property PACKAGE_PIN E9 [get_ports {QspiSCK}] #set_property IOSTANDARD LVCMOS33 [get_ports {QspiSCK}] ##Bank = CONFIG, Pin name = IO_L1P_T0_D00_MOSI_14, Sch name = QSPI_DQ0 -#set_property PACKAGE_PIN K17 [get_ports {QspiDB[0]}] +#set_property PACKAGE_PIN K17 [get_ports {QspiDB[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}] ##Bank = CONFIG, Pin name = IO_L1N_T0_D01_DIN_14, Sch name = QSPI_DQ1 -#set_property PACKAGE_PIN K18 [get_ports {QspiDB[1]}] +#set_property PACKAGE_PIN K18 [get_ports {QspiDB[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}] ##Bank = CONFIG, Pin name = IO_L20_T0_D02_14, Sch name = QSPI_DQ2 -#set_property PACKAGE_PIN L14 [get_ports {QspiDB[2]}] +#set_property PACKAGE_PIN L14 [get_ports {QspiDB[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}] ##Bank = CONFIG, Pin name = IO_L2P_T0_D03_14, Sch name = QSPI_DQ3 -#set_property PACKAGE_PIN M14 [get_ports {QspiDB[3]}] +#set_property PACKAGE_PIN M14 [get_ports {QspiDB[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}] ##Bank = CONFIG, Pin name = IO_L15N_T2_DQS_DOUT_CSO_B_14, Sch name = QSPI_CSN -#set_property PACKAGE_PIN L13 [get_ports QspiCSn] +#set_property PACKAGE_PIN L13 [get_ports QspiCSn] #set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn] ##Cellular RAM ##Bank = 14, Pin name = IO_L14N_T2_SRCC_14, Sch name = CRAM_CLK -#set_property PACKAGE_PIN T15 [get_ports RamCLK] +#set_property PACKAGE_PIN T15 [get_ports RamCLK] #set_property IOSTANDARD LVCMOS33 [get_ports RamCLK] ##Bank = 14, Pin name = IO_L23P_T3_A03_D19_14, Sch name = CRAM_ADVN -#set_property PACKAGE_PIN T13 [get_ports RamADVn] +#set_property PACKAGE_PIN T13 [get_ports RamADVn] #set_property IOSTANDARD LVCMOS33 [get_ports RamADVn] ##Bank = 14, Pin name = IO_L4P_T0_D04_14, Sch name = CRAM_CEN -#set_property PACKAGE_PIN L18 [get_ports RamCEn] +#set_property PACKAGE_PIN L18 [get_ports RamCEn] #set_property IOSTANDARD LVCMOS33 [get_ports RamCEn] ##Bank = 15, Pin name = IO_L19P_T3_A22_15, Sch name = CRAM_CRE -#set_property PACKAGE_PIN J14 [get_ports RamCRE] +#set_property PACKAGE_PIN J14 [get_ports RamCRE] #set_property IOSTANDARD LVCMOS33 [get_ports RamCRE] ##Bank = 15, Pin name = IO_L15P_T2_DQS_15, Sch name = CRAM_OEN -#set_property PACKAGE_PIN H14 [get_ports RamOEn] +#set_property PACKAGE_PIN H14 [get_ports RamOEn] #set_property IOSTANDARD LVCMOS33 [get_ports RamOEn] ##Bank = 14, Pin name = IO_0_14, Sch name = CRAM_WEN -#set_property PACKAGE_PIN R11 [get_ports RamWEn] +#set_property PACKAGE_PIN R11 [get_ports RamWEn] #set_property IOSTANDARD LVCMOS33 [get_ports RamWEn] ##Bank = 15, Pin name = IO_L24N_T3_RS0_15, Sch name = CRAM_LBN -#set_property PACKAGE_PIN J15 [get_ports RamLBn] +#set_property PACKAGE_PIN J15 [get_ports RamLBn] #set_property IOSTANDARD LVCMOS33 [get_ports RamLBn] ##Bank = 15, Pin name = IO_L17N_T2_A25_15, Sch name = CRAM_UBN -#set_property PACKAGE_PIN J13 [get_ports RamUBn] +#set_property PACKAGE_PIN J13 [get_ports RamUBn] #set_property IOSTANDARD LVCMOS33 [get_ports RamUBn] ##Bank = 14, Pin name = IO_L14P_T2_SRCC_14, Sch name = CRAM_WAIT -#set_property PACKAGE_PIN T14 [get_ports RamWait] +#set_property PACKAGE_PIN T14 [get_ports RamWait] #set_property IOSTANDARD LVCMOS33 [get_ports RamWait] ##Bank = 14, Pin name = IO_L5P_T0_DQ06_14, Sch name = CRAM_DQ0 -#set_property PACKAGE_PIN R12 [get_ports {MemDB[0]}] +#set_property PACKAGE_PIN R12 [get_ports {MemDB[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[0]}] ##Bank = 14, Pin name = IO_L19P_T3_A10_D26_14, Sch name = CRAM_DQ1 -#set_property PACKAGE_PIN T11 [get_ports {MemDB[1]}] +#set_property PACKAGE_PIN T11 [get_ports {MemDB[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[1]}] ##Bank = 14, Pin name = IO_L20P_T3_A08)D24_14, Sch name = CRAM_DQ2 -#set_property PACKAGE_PIN U12 [get_ports {MemDB[2]}] +#set_property PACKAGE_PIN U12 [get_ports {MemDB[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[2]}] ##Bank = 14, Pin name = IO_L5N_T0_D07_14, Sch name = CRAM_DQ3 -#set_property PACKAGE_PIN R13 [get_ports {MemDB[3]}] +#set_property PACKAGE_PIN R13 [get_ports {MemDB[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[3]}] ##Bank = 14, Pin name = IO_L17N_T2_A13_D29_14, Sch name = CRAM_DQ4 -#set_property PACKAGE_PIN U18 [get_ports {MemDB[4]}] +#set_property PACKAGE_PIN U18 [get_ports {MemDB[4]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[4]}] ##Bank = 14, Pin name = IO_L12N_T1_MRCC_14, Sch name = CRAM_DQ5 -#set_property PACKAGE_PIN R17 [get_ports {MemDB[5]}] +#set_property PACKAGE_PIN R17 [get_ports {MemDB[5]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[5]}] ##Bank = 14, Pin name = IO_L7N_T1_D10_14, Sch name = CRAM_DQ6 -#set_property PACKAGE_PIN T18 [get_ports {MemDB[6]}] +#set_property PACKAGE_PIN T18 [get_ports {MemDB[6]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[6]}] ##Bank = 14, Pin name = IO_L7P_T1_D09_14, Sch name = CRAM_DQ7 -#set_property PACKAGE_PIN R18 [get_ports {MemDB[7]}] +#set_property PACKAGE_PIN R18 [get_ports {MemDB[7]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[7]}] ##Bank = 15, Pin name = IO_L22N_T3_A16_15, Sch name = CRAM_DQ8 -#set_property PACKAGE_PIN F18 [get_ports {MemDB[8]}] +#set_property PACKAGE_PIN F18 [get_ports {MemDB[8]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[8]}] ##Bank = 15, Pin name = IO_L22P_T3_A17_15, Sch name = CRAM_DQ9 -#set_property PACKAGE_PIN G18 [get_ports {MemDB[9]}] +#set_property PACKAGE_PIN G18 [get_ports {MemDB[9]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[9]}] ##Bank = 15, Pin name = IO_IO_L18N_T2_A23_15, Sch name = CRAM_DQ10 -#set_property PACKAGE_PIN G17 [get_ports {MemDB[10]}] +#set_property PACKAGE_PIN G17 [get_ports {MemDB[10]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[10]}] ##Bank = 14, Pin name = IO_L4N_T0_D05_14, Sch name = CRAM_DQ11 -#set_property PACKAGE_PIN M18 [get_ports {MemDB[11]}] +#set_property PACKAGE_PIN M18 [get_ports {MemDB[11]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[11]}] ##Bank = 14, Pin name = IO_L10N_T1_D15_14, Sch name = CRAM_DQ12 -#set_property PACKAGE_PIN M17 [get_ports {MemDB[12]}] +#set_property PACKAGE_PIN M17 [get_ports {MemDB[12]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[12]}] ##Bank = 14, Pin name = IO_L9N_T1_DQS_D13_14, Sch name = CRAM_DQ13 -#set_property PACKAGE_PIN P18 [get_ports {MemDB[13]}] +#set_property PACKAGE_PIN P18 [get_ports {MemDB[13]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[13]}] ##Bank = 14, Pin name = IO_L9P_T1_DQS_14, Sch name = CRAM_DQ14 -#set_property PACKAGE_PIN N17 [get_ports {MemDB[14]}] +#set_property PACKAGE_PIN N17 [get_ports {MemDB[14]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[14]}] ##Bank = 14, Pin name = IO_L12P_T1_MRCC_14, Sch name = CRAM_DQ15 -#set_property PACKAGE_PIN P17 [get_ports {MemDB[15]}] +#set_property PACKAGE_PIN P17 [get_ports {MemDB[15]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[15]}] ##Bank = 15, Pin name = IO_L23N_T3_FWE_B_15, Sch name = CRAM_A0 -#set_property PACKAGE_PIN J18 [get_ports {MemAdr[0]}] +#set_property PACKAGE_PIN J18 [get_ports {MemAdr[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[0]}] ##Bank = 15, Pin name = IO_L18P_T2_A24_15, Sch name = CRAM_A1 -#set_property PACKAGE_PIN H17 [get_ports {MemAdr[1]}] +#set_property PACKAGE_PIN H17 [get_ports {MemAdr[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[1]}] ##Bank = 15, Pin name = IO_L19N_T3_A21_VREF_15, Sch name = CRAM_A2 -#set_property PACKAGE_PIN H15 [get_ports {MemAdr[2]}] +#set_property PACKAGE_PIN H15 [get_ports {MemAdr[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[2]}] ##Bank = 15, Pin name = IO_L23P_T3_FOE_B_15, Sch name = CRAM_A3 -#set_property PACKAGE_PIN J17 [get_ports {MemAdr[3]}] +#set_property PACKAGE_PIN J17 [get_ports {MemAdr[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[3]}] ##Bank = 15, Pin name = IO_L13P_T2_MRCC_15, Sch name = CRAM_A4 -#set_property PACKAGE_PIN H16 [get_ports {MemAdr[4]}] +#set_property PACKAGE_PIN H16 [get_ports {MemAdr[4]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[4]}] ##Bank = 15, Pin name = IO_L24P_T3_RS1_15, Sch name = CRAM_A5 -#set_property PACKAGE_PIN K15 [get_ports {MemAdr[5]}] +#set_property PACKAGE_PIN K15 [get_ports {MemAdr[5]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[5]}] ##Bank = 15, Pin name = IO_L17P_T2_A26_15, Sch name = CRAM_A6 -#set_property PACKAGE_PIN K13 [get_ports {MemAdr[6]}] +#set_property PACKAGE_PIN K13 [get_ports {MemAdr[6]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[6]}] ##Bank = 14, Pin name = IO_L11P_T1_SRCC_14, Sch name = CRAM_A7 -#set_property PACKAGE_PIN N15 [get_ports {MemAdr[7]}] +#set_property PACKAGE_PIN N15 [get_ports {MemAdr[7]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[7]}] ##Bank = 14, Pin name = IO_L16N_T2_SRCC-14, Sch name = CRAM_A8 -#set_property PACKAGE_PIN V16 [get_ports {MemAdr[8]}] +#set_property PACKAGE_PIN V16 [get_ports {MemAdr[8]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[8]}] ##Bank = 14, Pin name = IO_L22P_T3_A05_D21_14, Sch name = CRAM_A9 -#set_property PACKAGE_PIN U14 [get_ports {MemAdr[9]}] +#set_property PACKAGE_PIN U14 [get_ports {MemAdr[9]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[9]}] ##Bank = 14, Pin name = IO_L22N_T3_A04_D20_14, Sch name = CRAM_A10 -#set_property PACKAGE_PIN V14 [get_ports {MemAdr[10]}] +#set_property PACKAGE_PIN V14 [get_ports {MemAdr[10]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[10]}] ##Bank = 14, Pin name = IO_L20N_T3_A07_D23_14, Sch name = CRAM_A11 -#set_property PACKAGE_PIN V12 [get_ports {MemAdr[11]}] +#set_property PACKAGE_PIN V12 [get_ports {MemAdr[11]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[11]}] ##Bank = 14, Pin name = IO_L8N_T1_D12_14, Sch name = CRAM_A12 -#set_property PACKAGE_PIN P14 [get_ports {MemAdr[12]}] +#set_property PACKAGE_PIN P14 [get_ports {MemAdr[12]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[12]}] ##Bank = 14, Pin name = IO_L18P_T2_A12_D28_14, Sch name = CRAM_A13 -#set_property PACKAGE_PIN U16 [get_ports {MemAdr[13]}] +#set_property PACKAGE_PIN U16 [get_ports {MemAdr[13]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[13]}] ##Bank = 14, Pin name = IO_L13N_T2_MRCC_14, Sch name = CRAM_A14 -#set_property PACKAGE_PIN R15 [get_ports {MemAdr[14]}] +#set_property PACKAGE_PIN R15 [get_ports {MemAdr[14]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[14]}] ##Bank = 14, Pin name = IO_L8P_T1_D11_14, Sch name = CRAM_A15 -#set_property PACKAGE_PIN N14 [get_ports {MemAdr[15]}] +#set_property PACKAGE_PIN N14 [get_ports {MemAdr[15]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[15]}] ##Bank = 14, Pin name = IO_L11N_T1_SRCC_14, Sch name = CRAM_A16 -#set_property PACKAGE_PIN N16 [get_ports {MemAdr[16]}] +#set_property PACKAGE_PIN N16 [get_ports {MemAdr[16]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[16]}] ##Bank = 14, Pin name = IO_L6N_T0_D08_VREF_14, Sch name = CRAM_A17 -#set_property PACKAGE_PIN M13 [get_ports {MemAdr[17]}] +#set_property PACKAGE_PIN M13 [get_ports {MemAdr[17]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[17]}] ##Bank = 14, Pin name = IO_L18N_T2_A11_D27_14, Sch name = CRAM_A18 -#set_property PACKAGE_PIN V17 [get_ports {MemAdr[18]}] +#set_property PACKAGE_PIN V17 [get_ports {MemAdr[18]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[18]}] ##Bank = 14, Pin name = IO_L17P_T2_A14_D30_14, Sch name = CRAM_A19 -#set_property PACKAGE_PIN U17 [get_ports {MemAdr[19]}] +#set_property PACKAGE_PIN U17 [get_ports {MemAdr[19]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[19]}] ##Bank = 14, Pin name = IO_L24N_T3_A00_D16_14, Sch name = CRAM_A20 -#set_property PACKAGE_PIN T10 [get_ports {MemAdr[20]}] +#set_property PACKAGE_PIN T10 [get_ports {MemAdr[20]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[20]}] ##Bank = 14, Pin name = IO_L10P_T1_D14_14, Sch name = CRAM_A21 -#set_property PACKAGE_PIN M16 [get_ports {MemAdr[21]}] - #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[21]}] +#set_property PACKAGE_PIN M16 [get_ports {MemAdr[21]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[21]}] ##Bank = 14, Pin name = IO_L23N_T3_A02_D18_14, Sch name = CRAM_A22 -#set_property PACKAGE_PIN U13 [get_ports {MemAdr[22]}] - #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[22]}] \ No newline at end of file +#set_property PACKAGE_PIN U13 [get_ports {MemAdr[22]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[22]}] From 75e722b22242814e2dbceceeb7ecb75414337212 Mon Sep 17 00:00:00 2001 From: yannickreiss Date: Tue, 26 Sep 2023 11:34:53 +0200 Subject: [PATCH 07/16] Implement ALU --- fpga/src/alu.vhd | 63 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/fpga/src/alu.vhd b/fpga/src/alu.vhd index e69de29..35e1808 100644 --- a/fpga/src/alu.vhd +++ b/fpga/src/alu.vhd @@ -0,0 +1,63 @@ +-- alu.vhd +-- Created on: Di 26. Sep 10:07:59 CEST 2023 +-- Author(s): Yannick Reiß +-- Content: Decode instructions and control brainfuck logic +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- Entity alu: alu crtl +entity alu is + port( + instruction : in std_logic_vector(2 downto 0); + old_cell : in std_logic_vector(7 downto 0); + old_pointer : in std_logic_vector(15 downto 0); + extern_in : in std_logic_vector(7 downto 0); + + new_cell : out std_logic_vector(7 downto 0); + new_pointer : out std_logic_vector(15 downto 0); + enable_cell : out std_logic; + enable_ptr : out std_logic; + extern_out : out std_logic_vector(7 downto 0) + ); +end alu; + +-- Architecture implementation of alu: implements table +architecture implementation of alu is + +begin + -- Process p_instruction + p_instruction : process (instruction) -- runs only, when instruction changed + begin + case instruction is + when "000" => + enable_cell <= '0'; + enable_ptr <= '1'; + new_pointer <= std_logic_vector(unsigned(old_pointer) + 1); + when "001" => + enable_cell <= '0'; + enable_ptr <= '1'; + new_pointer <= std_logic_vector(unsigned(old_pointer) - 1); + when "010" => + enable_cell <= '1'; + enable_ptr <= '0'; + new_cell <= std_logic_vector(unsigned(old_cell) + 1); + when "011" => + enable_cell <= '1'; + enable_ptr <= '0'; + new_cell <= std_logic_vector(unsigned(old_cell) - 1); + when "100" => + enable_cell <= '1'; + enable_ptr <= '0'; + new_cell <= extern_in; + when "101" => + enable_cell <= '0'; + enable_ptr <= '0'; + extern_out <= old_cell; + when others => + enable_cell <= '0'; + enable_ptr <= '0'; + end case; + end process; + +end implementation; From 090cd8c07a748ddd54f2f459b63f2cfac90a6e0d Mon Sep 17 00:00:00 2001 From: yannickreiss Date: Tue, 26 Sep 2023 11:36:50 +0200 Subject: [PATCH 08/16] Implement instruction memory --- fpga/src/instructionMemory.vhd | 37 ++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/fpga/src/instructionMemory.vhd b/fpga/src/instructionMemory.vhd index e69de29..aa9c6c7 100644 --- a/fpga/src/instructionMemory.vhd +++ b/fpga/src/instructionMemory.vhd @@ -0,0 +1,37 @@ +-- instructionMemory.vhd +-- Created on: Di 26. Sep 07:43:20 CEST 2023 +-- Author(s): Yannick Reiß +-- Content: Instruction memory; Read and write operations are controlled externally. +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- Entity instructionMemory: Currently ROM; TODO: Add write enable when implementing a bus. +entity instructionMemory is + + port( + clk : in std_logic; -- clock with speed of board clock; Read on clock cycle + instructionAddr : in std_logic_vector(7 downto 0); -- We start with 256 instructions + + instruction : out std_logic_vector(2 downto 0) -- instruction in current cell + ); +end instructionMemory; + +-- Architecture arch of instructionMemory: read on every clock cycle to instruction. +architecture arch of instructionMemory is + type imem is array(0 to 255) of std_logic_vector(2 downto 0); + + signal memory : imem := (b"000", b"001", b"010", b"011", b"100", b"101", b"110", b"111", others => "000"); +begin + -- Process clk_read + clk_read : process (clk) -- runs only, when clk changed + begin + + if rising_edge(clk) then + + instruction <= memory(to_integer(unsigned(instructionAddr))); + + end if; + end process; + +end arch; From 74c4ea39b5e0780103322e2728c45d6d1d398364 Mon Sep 17 00:00:00 2001 From: yannickreiss Date: Tue, 26 Sep 2023 11:37:06 +0200 Subject: [PATCH 09/16] No need for decoder --- fpga/src/decoder.vhd | 0 1 file changed, 0 insertions(+), 0 deletions(-) delete mode 100644 fpga/src/decoder.vhd diff --git a/fpga/src/decoder.vhd b/fpga/src/decoder.vhd deleted file mode 100644 index e69de29..0000000 From bccd638d2b1f27a464d090db8a81cc1e6ca08ddf Mon Sep 17 00:00:00 2001 From: yannickreiss Date: Tue, 26 Sep 2023 11:37:27 +0200 Subject: [PATCH 10/16] Implement brainfuck ptr --- fpga/src/memoryPointer.vhd | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/fpga/src/memoryPointer.vhd b/fpga/src/memoryPointer.vhd index e69de29..141395b 100644 --- a/fpga/src/memoryPointer.vhd +++ b/fpga/src/memoryPointer.vhd @@ -0,0 +1,35 @@ +-- memoryPointer.vhd +-- Created on: Di 26. Sep 11:11:49 CEST 2023 +-- Author(s): Yannick Reiß +-- Content: Store current ptr. Part of brainfuck logic +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- Entity ptr: 15 bit pointer to cell +entity ptr is + port( + clk : in std_logic; + enable_ptr : in std_logic; + new_ptr : in std_logic_vector(15 downto 0); + + old_ptr : out std_logic_vector(15 downto 0) + ); +end ptr; + +-- Architecture implement_ptr of ptr: +architecture implement_ptr of ptr is + signal reg : std_logic_vector(15 downto 0); +begin + + -- Process Write set new_ptr + write : process (clk) -- runs only, when clk changed + begin + if rising_edge(clk) and enable_ptr = '1' then + reg <= new_ptr; + end if; + end process; + + old_ptr <= reg; + +end implement_ptr; From 51fe976188ac5042b72731abc01e1e6ebf56fb9e Mon Sep 17 00:00:00 2001 From: yannickreiss Date: Tue, 26 Sep 2023 11:37:47 +0200 Subject: [PATCH 11/16] Rushed implementation connecting parts --- fpga/src/bfpu.vhd | 98 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 98 insertions(+) diff --git a/fpga/src/bfpu.vhd b/fpga/src/bfpu.vhd index e69de29..c85e7c4 100644 --- a/fpga/src/bfpu.vhd +++ b/fpga/src/bfpu.vhd @@ -0,0 +1,98 @@ +-- bfpu.vhd +-- Created on: Di 26. Sep 08:27:47 CEST 2023 +-- Author(s): Yannick Reiß +-- Content: Connect the entities of the processing unit. +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- Entity bfpu: brainfuck processing unit +entity bfpu is + port( + clk : in std_logic; -- board clock + sw : in std_logic_vector(7 downto 0); -- Input for instruction , + led : out std_logic_vector(7 downto 0) -- Output for instruction . + ); +end bfpu; + +-- Architecture arch of bfpu: setup and connect components +architecture arch of bfpu is + + component instructionMemory + port( + clk : in std_logic; + instructionAddr : in std_logic_vector(7 downto 0); + instruction : out std_logic_vector(2 downto 0) + ); + end component; + + component alu + port( + instruction : in std_logic_vector(2 downto 0); + old_cell : in std_logic_vector(7 downto 0); + old_pointer : in std_logic_vector(15 downto 0); + extern_in : in std_logic_vector(7 downto 0); + + new_cell : out std_logic_vector(7 downto 0); + new_pointer : out std_logic_vector(15 downto 0); + enable_cell : out std_logic; + enable_ptr : out std_logic; + extern_out : out std_logic_vector(7 downto 0) + ); + end component; + + component ptr + port( + clk : in std_logic; + enable_ptr : in std_logic; + new_ptr : in std_logic_vector(15 downto 0); + old_ptr : out std_logic_vector(15 downto 0) + ); + end component; + + signal s_clk : std_logic; + signal s_instrAddr : std_logic_vector(7 downto 0); + signal s_instruction : std_logic_vector(2 downto 0); + + signal s_cell_out : std_logic_vector(7 downto 0); + signal s_cell_in : std_logic_vector(7 downto 0); + signal s_ptr_out : std_logic_vector(15 downto 0); + signal s_ptr_in : std_logic_vector(15 downto 0); + + signal s_enable_cells : std_logic; + signal s_enable_ptr : std_logic; + +begin + + s_clk <= clk; + + instrMemory : instructionMemory + port map( + clk => s_clk, + instructionAddr => s_instrAddr, + instruction => s_instruction + ); + + alu_entity : alu + port map( + instruction => s_instruction, + old_cell => s_cell_out, + old_pointer => s_ptr_out, + extern_in => sw, + + new_cell => s_cell_in, + new_pointer => s_ptr_in, + enable_cell => s_enable_cells, + enable_ptr => s_enable_ptr, + extern_out => led + ); + + ptr_bf : ptr + port map( + clk => s_clk, + enable_ptr => s_enable_ptr, + new_ptr => s_ptr_in, + old_ptr => s_ptr_out + ); + +end arch; From d27378e58f32f81bb35f1407b2ffe2d613c6aa0b Mon Sep 17 00:00:00 2001 From: yannickreiss Date: Tue, 26 Sep 2023 12:03:53 +0200 Subject: [PATCH 12/16] Implement cell memory --- fpga/src/bfpu.vhd | 19 +++++++++++++++++++ fpga/src/cellMemory.vhd | 42 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 61 insertions(+) diff --git a/fpga/src/bfpu.vhd b/fpga/src/bfpu.vhd index c85e7c4..06ffd13 100644 --- a/fpga/src/bfpu.vhd +++ b/fpga/src/bfpu.vhd @@ -50,6 +50,16 @@ architecture arch of bfpu is ); end component; + component cellblock + port( + clk : in std_logic; + enable : in std_logic; + address : in std_logic_vector(15 downto 0); + new_cell : in std_logic_vector(7 downto 0); + old_cell : out std_logic_vector(7 downto 0) + ); + end component; + signal s_clk : std_logic; signal s_instrAddr : std_logic_vector(7 downto 0); signal s_instruction : std_logic_vector(2 downto 0); @@ -95,4 +105,13 @@ begin old_ptr => s_ptr_out ); + cellblock_bf : cellblock + port map( + clk => s_clk, + enable => s_enable_cells, + address => s_ptr_out, + new_cell => s_cell_in, + old_cell => s_cell_out + ); + end arch; diff --git a/fpga/src/cellMemory.vhd b/fpga/src/cellMemory.vhd index e69de29..b7da2d6 100644 --- a/fpga/src/cellMemory.vhd +++ b/fpga/src/cellMemory.vhd @@ -0,0 +1,42 @@ +-- cellMemory.vhd +-- Created on: Di 26. Sep 11:39:10 CEST 2023 +-- Author(s): Yannick Reiß +-- Content: Cell memory as part of brainfuck logic +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +-- Entity cellblock +entity cellblock is + + port( + clk : in std_logic; -- clock with speed of board clock + enable : in std_logic; + address : in std_logic_vector(15 downto 0); + new_cell : in std_logic_vector(7 downto 0); + + old_cell : out std_logic_vector(7 downto 0) + ); +end cellblock; + +-- Architecture arch of cellblock: read on every clock cycle to cell. +architecture arch of cellblock is + type empty is array(0 to 65536) of std_logic_vector(7 downto 0); + + signal memory : empty := (others => (others => '0')); + +begin + -- Process clk_read + clk_read : process (clk) -- runs only, when clk changed + begin + + if rising_edge(clk) and enable = '1' then + memory(to_integer(unsigned(address))) <= new_cell; + end if; + + end process; + + old_cell <= memory(to_integer(unsigned(address))); + +end arch; From 180caa0b3cef977b33a102c93a11784889fed414 Mon Sep 17 00:00:00 2001 From: yannickreiss Date: Tue, 26 Sep 2023 14:14:18 +0200 Subject: [PATCH 13/16] Implement program memory --- fpga/src/bfpu.vhd | 23 +++++++++++++++++++++ fpga/src/programCounter.vhd | 40 +++++++++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+) diff --git a/fpga/src/bfpu.vhd b/fpga/src/bfpu.vhd index 06ffd13..6f0936f 100644 --- a/fpga/src/bfpu.vhd +++ b/fpga/src/bfpu.vhd @@ -60,6 +60,16 @@ architecture arch of bfpu is ); end component; + component program_counter + port( + clk : in std_logic; + enable : in std_logic; + jmp : in std_logic; + pc_in : in std_logic_vector(7 downto 0); + pc_out : out std_logic_vector(7 downto 0) + ); + end component; + signal s_clk : std_logic; signal s_instrAddr : std_logic_vector(7 downto 0); signal s_instruction : std_logic_vector(2 downto 0); @@ -72,6 +82,10 @@ architecture arch of bfpu is signal s_enable_cells : std_logic; signal s_enable_ptr : std_logic; + signal s_enable_pc : std_logic; + signal s_jmp_pc : std_logic; + signal s_jmp_addr_pc : std_logic_vector(7 downto 0); + begin s_clk <= clk; @@ -114,4 +128,13 @@ begin old_cell => s_cell_out ); + pc : program_counter + port map( + clk => s_clk, + enable => s_enable_pc, + jmp => s_jmp_pc, + pc_in => s_jmp_addr_pc, + pc_out => s_instrAddr + ); + end arch; diff --git a/fpga/src/programCounter.vhd b/fpga/src/programCounter.vhd index e69de29..5846e07 100644 --- a/fpga/src/programCounter.vhd +++ b/fpga/src/programCounter.vhd @@ -0,0 +1,40 @@ +-- programCounter.vhd +-- Created on: Di 26. Sep 12:45:10 CEST 2023 +-- Author(s): Yannick Reiß +-- Content: Set and store program counter only. Logic entirely in branch! +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- Entity program_counter: set/store pc +entity program_counter is + port( + clk : in std_logic; + enable : in std_logic; + jmp : in std_logic; + pc_in : in std_logic_vector(7 downto 0); + pc_out : out std_logic_vector(7 downto 0) + ); +end program_counter; + +-- Architecture pc of program_counter: +architecture pc of program_counter is + signal pc_intern : std_logic_vector(7 downto 0) := (others => '0'); +begin + + -- Process count + count : process (clk, enable, jmp) -- runs only, when clk, enable, jmp changed + begin + if rising_edge(clk) and enable = '1' then + if jmp = '1' then + pc_intern <= pc_in; + else + pc_intern <= std_logic_vector(unsigned(pc_intern) + 1); + end if; + end if; + end process; + + + pc_out <= pc_intern; + +end pc; From 30559c81a9d3d9e266da22dc4d84c702869d7edd Mon Sep 17 00:00:00 2001 From: yannickreiss Date: Tue, 26 Sep 2023 20:42:36 +0200 Subject: [PATCH 14/16] Implementation of branch, excluding stack --- fpga/src/bfpu.vhd | 36 +++++++++++++++++- fpga/src/branch.vhd | 90 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 124 insertions(+), 2 deletions(-) diff --git a/fpga/src/bfpu.vhd b/fpga/src/bfpu.vhd index 6f0936f..848bc00 100644 --- a/fpga/src/bfpu.vhd +++ b/fpga/src/bfpu.vhd @@ -70,9 +70,23 @@ architecture arch of bfpu is ); end component; + component branch + port( + clk : in std_logic; + instruction : in std_logic_vector(2 downto 0); + instr_addr : in std_logic_vector(7 downto 0); + cell_value : in std_logic_vector(7 downto 0); + + skip : out std_logic; + pc_enable : out std_logic; + pc_out : out std_logic_vector(7 downto 0) + ); + end component; + signal s_clk : std_logic; signal s_instrAddr : std_logic_vector(7 downto 0); signal s_instruction : std_logic_vector(2 downto 0); + signal s_instrAddr_branch : std_logic_vector(7 downto 0); signal s_cell_out : std_logic_vector(7 downto 0); signal s_cell_in : std_logic_vector(7 downto 0); @@ -86,6 +100,10 @@ architecture arch of bfpu is signal s_jmp_pc : std_logic; signal s_jmp_addr_pc : std_logic_vector(7 downto 0); + signal s_skip : std_logic; + signal s_enable_cells_o : std_logic; + signal s_enable_ptr_o : std_logic; + begin s_clk <= clk; @@ -106,8 +124,8 @@ begin new_cell => s_cell_in, new_pointer => s_ptr_in, - enable_cell => s_enable_cells, - enable_ptr => s_enable_ptr, + enable_cell => s_enable_cells_o, + enable_ptr => s_enable_ptr_o, extern_out => led ); @@ -137,4 +155,18 @@ begin pc_out => s_instrAddr ); + branch_bf : branch + port map( + clk => s_clk, + instruction => s_instruction, + instr_addr => s_instrAddr, + cell_value => s_cell_out, + skip => s_skip, + pc_enable => s_enable_pc, + pc_out => s_instrAddr_branch + ); + + s_enable_ptr <= s_skip and s_enable_ptr_o; + s_enable_cells <= s_skip and s_enable_cells_o; + end arch; diff --git a/fpga/src/branch.vhd b/fpga/src/branch.vhd index e69de29..e4e6dbc 100644 --- a/fpga/src/branch.vhd +++ b/fpga/src/branch.vhd @@ -0,0 +1,90 @@ +-- branch.vhd +-- Created on: Di 26. Sep 13:47:51 CEST 2023 +-- Author(s): Yannick Reiss +-- Content: Branch unit / ALU for program counter XD +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- Entity branch: branch +entity branch is + port( + clk : in std_logic; + instruction : in std_logic_vector(2 downto 0); + instr_addr : in std_logic_vector(7 downto 0); + cell_value : in std_logic_vector(7 downto 0); + + skip : out std_logic; + pc_enable : out std_logic; + pc_out : out std_logic_vector(7 downto 0) + ); +end branch; + +-- Architecture impl of branch: +architecture impl of branch is + type stack is array(0 to 255) of std_logic_vector(7 downto 0); + + signal addr_stack : stack := (others => (others => '0')); + signal nested : std_logic_vector(7 downto 0) := (others => '0'); -- count nested loops + signal jump_destination : std_logic_vector(7 downto 0); + signal skip_internal : std_logic := '0'; + signal stack_ptr : std_logic_vector(7 downto 0) := (others => '0'); + signal push_state : std_logic; + +begin + + -- Process p_skip: set skip to true + p_skip : process (clk) + begin + if rising_edge(clk) then + if instruction = "110" and unsigned(cell_value) = 0 and unsigned(nested) = 0 and skip_internal = '0' then + skip_internal <= '1'; + end if; + end if; + end process; + + -- Process p_continue: set skip to false + p_continue : process (clk) + begin + if rising_edge(clk) then + if instruction = "111" and unsigned(nested) = 0 and skip_internal = '1' then + skip_internal <= '0'; + end if; + end if; + end process; + + -- Process p_nest : raise nest by one as [ is passed + p_nest : process (clk) + begin + if rising_edge(clk) then + if instruction = "110" and skip_internal = '1' then + nested <= std_logic_vector(unsigned(nested) + 1); + end if; + end if; + end process; + + -- Process p_unnest : lower nest, as ] is passed + p_unnest : process (clk) + begin + if rising_edge(clk) then + if instruction = "111" and unsigned(nested) > 0 and skip_internal = '1' then + nested <= std_logic_vector(unsigned(nested) - 1); + end if; + end if; + end process; + + -- Process p_push : raise stack and push address + p_push : process (clk) + begin + -- TODO: Implement + end process; + + -- Process p_pop : read address to jump address and lower stack + p_pop : process (clk) + begin + -- TODO: Implement + end process; + + skip <= skip_internal; + +end impl; From f906a6e4a3f5af7f8187a6e33287253fd484e70b Mon Sep 17 00:00:00 2001 From: yannickreiss Date: Wed, 27 Sep 2023 20:44:03 +0200 Subject: [PATCH 15/16] Implement push and pop in branch --- fpga/src/bfpu.vhd | 5 +++-- fpga/src/branch.vhd | 53 ++++++++++++++++++++++++++++++++++++--------- 2 files changed, 46 insertions(+), 12 deletions(-) diff --git a/fpga/src/bfpu.vhd b/fpga/src/bfpu.vhd index 848bc00..ff6d86c 100644 --- a/fpga/src/bfpu.vhd +++ b/fpga/src/bfpu.vhd @@ -78,6 +78,7 @@ architecture arch of bfpu is cell_value : in std_logic_vector(7 downto 0); skip : out std_logic; + jump : out std_logic; pc_enable : out std_logic; pc_out : out std_logic_vector(7 downto 0) ); @@ -86,7 +87,6 @@ architecture arch of bfpu is signal s_clk : std_logic; signal s_instrAddr : std_logic_vector(7 downto 0); signal s_instruction : std_logic_vector(2 downto 0); - signal s_instrAddr_branch : std_logic_vector(7 downto 0); signal s_cell_out : std_logic_vector(7 downto 0); signal s_cell_in : std_logic_vector(7 downto 0); @@ -162,8 +162,9 @@ begin instr_addr => s_instrAddr, cell_value => s_cell_out, skip => s_skip, + jump => s_jmp_pc, pc_enable => s_enable_pc, - pc_out => s_instrAddr_branch + pc_out => s_jmp_addr_pc ); s_enable_ptr <= s_skip and s_enable_ptr_o; diff --git a/fpga/src/branch.vhd b/fpga/src/branch.vhd index e4e6dbc..cf7c1c7 100644 --- a/fpga/src/branch.vhd +++ b/fpga/src/branch.vhd @@ -16,6 +16,7 @@ entity branch is skip : out std_logic; pc_enable : out std_logic; + jump : out std_logic; pc_out : out std_logic_vector(7 downto 0) ); end branch; @@ -26,10 +27,9 @@ architecture impl of branch is signal addr_stack : stack := (others => (others => '0')); signal nested : std_logic_vector(7 downto 0) := (others => '0'); -- count nested loops - signal jump_destination : std_logic_vector(7 downto 0); signal skip_internal : std_logic := '0'; signal stack_ptr : std_logic_vector(7 downto 0) := (others => '0'); - signal push_state : std_logic; + signal push_state : std_logic := '1'; begin @@ -42,7 +42,7 @@ begin end if; end if; end process; - + -- Process p_continue: set skip to false p_continue : process (clk) begin @@ -52,7 +52,7 @@ begin end if; end if; end process; - + -- Process p_nest : raise nest by one as [ is passed p_nest : process (clk) begin @@ -62,7 +62,7 @@ begin end if; end if; end process; - + -- Process p_unnest : lower nest, as ] is passed p_unnest : process (clk) begin @@ -72,19 +72,52 @@ begin end if; end if; end process; - + -- Process p_push : raise stack and push address p_push : process (clk) begin - -- TODO: Implement + if rising_edge(clk) and instruction = "110" and unsigned(cell_value) > 0 and skip_internal = '0' then + if push_state = '0' then + -- restore push_state and push address + addr_stack(to_integer(unsigned(stack_ptr))) <= instr_addr; + push_state <= '1'; + pc_enable <= '1'; + else + -- raise stack, disable pc and unset push_state + stack_ptr <= std_logic_vector(unsigned(stack_ptr) + 1); + pc_enable <= '0'; + push_state <= '0'; + end if; + end if; end process; - + -- Process p_pop : read address to jump address and lower stack p_pop : process (clk) begin - -- TODO: Implement + if rising_edge(clk) and instruction = "111" and unsigned(cell_value) > 0 and skip_internal = '0' then + if push_state = '1' then + -- set address to pc_out, disable pc and unset push_state + pc_out <= addr_stack(to_integer(unsigned(stack_ptr))); + pc_enable <= '0'; + push_state <= '0'; + else + -- set pc to enabled, restore push_state and lower stack + pc_enable <= '1'; + push_state <= '1'; + stack_ptr <= std_logic_vector(unsigned(stack_ptr) - 1); + end if; + end if; + + -- regulate jump + if rising_edge(clk) then + if instruction = "111" and unsigned(cell_value) > 0 and skip_internal = '0' and push_state = '0' then + jump <= '1'; + else + jump <= '0'; + end if; + end if; end process; - + skip <= skip_internal; end impl; From 1b4f753c5454a3fc6b2b052694b7f954c13ad8a0 Mon Sep 17 00:00:00 2001 From: yannickreiss Date: Wed, 4 Oct 2023 11:27:25 +0200 Subject: [PATCH 16/16] First working implementation --- fpga/constrainits.xdc | 48 +++++++++++++++++----------------- fpga/src/alu.vhd | 30 ++++++++++++++++++--- fpga/src/bfpu.vhd | 2 ++ fpga/src/branch.vhd | 46 ++++++++++---------------------- fpga/src/cellMemory.vhd | 2 +- fpga/src/instructionMemory.vhd | 5 ++-- fpga/src/memoryPointer.vhd | 2 +- fpga/src/programCounter.vhd | 2 +- 8 files changed, 73 insertions(+), 64 deletions(-) diff --git a/fpga/constrainits.xdc b/fpga/constrainits.xdc index 463edd0..9dec428 100755 --- a/fpga/constrainits.xdc +++ b/fpga/constrainits.xdc @@ -86,30 +86,30 @@ set_property PACKAGE_PIN U7 [get_ports {led[6]}] #Bank = 34, Pin name = IO_L22N_T3_34, Sch name = LED7 set_property PACKAGE_PIN U6 [get_ports {led[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}] -##Bank = 34, Pin name = IO_L10N_T1_34, Sch name = LED8 -#set_property PACKAGE_PIN V4 [get_ports {led[8]}] -# set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}] -##Bank = 34, Pin name = IO_L8N_T1_34, Sch name = LED9 -#set_property PACKAGE_PIN U3 [get_ports {led[9]}] -# set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}] -##Bank = 34, Pin name = IO_L7N_T1_34, Sch name = LED10 -#set_property PACKAGE_PIN V1 [get_ports {led[10]}] -# set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}] -##Bank = 34, Pin name = IO_L17P_T2_34, Sch name = LED11 -#set_property PACKAGE_PIN R1 [get_ports {led[11]}] -# set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}] -##Bank = 34, Pin name = IO_L13N_T2_MRCC_34, Sch name = LED12 -#set_property PACKAGE_PIN P5 [get_ports {led[12]}] -# set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}] -##Bank = 34, Pin name = IO_L7P_T1_34, Sch name = LED13 -#set_property PACKAGE_PIN U1 [get_ports {led[13]}] -# set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}] -##Bank = 34, Pin name = IO_L15N_T2_DQS_34, Sch name = LED14 -#set_property PACKAGE_PIN R2 [get_ports {led[14]}] -# set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}] -##Bank = 34, Pin name = IO_L15P_T2_DQS_34, Sch name = LED15 -#set_property PACKAGE_PIN P2 [get_ports {led[15]}] -# set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}] +#Bank = 34, Pin name = IO_L10N_T1_34, Sch name = LED8 +set_property PACKAGE_PIN V4 [get_ports {debug[0]}] + set_property IOSTANDARD LVCMOS33 [get_ports {debug[0]}] +#Bank = 34, Pin name = IO_L8N_T1_34, Sch name = LED9 +set_property PACKAGE_PIN U3 [get_ports {debug[1]}] + set_property IOSTANDARD LVCMOS33 [get_ports {debug[1]}] +#Bank = 34, Pin name = IO_L7N_T1_34, Sch name = LED10 +set_property PACKAGE_PIN V1 [get_ports {debug[2]}] + set_property IOSTANDARD LVCMOS33 [get_ports {debug[2]}] +#Bank = 34, Pin name = IO_L17P_T2_34, Sch name = LED11 +set_property PACKAGE_PIN R1 [get_ports {debug[3]}] + set_property IOSTANDARD LVCMOS33 [get_ports {debug[3]}] +#Bank = 34, Pin name = IO_L13N_T2_MRCC_34, Sch name = LED12 +set_property PACKAGE_PIN P5 [get_ports {debug[4]}] + set_property IOSTANDARD LVCMOS33 [get_ports {debug[4]}] +#Bank = 34, Pin name = IO_L7P_T1_34, Sch name = LED13 +set_property PACKAGE_PIN U1 [get_ports {debug[5]}] + set_property IOSTANDARD LVCMOS33 [get_ports {debug[5]}] +#Bank = 34, Pin name = IO_L15N_T2_DQS_34, Sch name = LED14 +set_property PACKAGE_PIN R2 [get_ports {debug[6]}] + set_property IOSTANDARD LVCMOS33 [get_ports {debug[6]}] +#Bank = 34, Pin name = IO_L15P_T2_DQS_34, Sch name = LED15 +set_property PACKAGE_PIN P2 [get_ports {debug[7]}] + set_property IOSTANDARD LVCMOS33 [get_ports {debug[7]}] ##Bank = 34, Pin name = IO_L5P_T0_34, Sch name = LED16_R #set_property PACKAGE_PIN K5 [get_ports {rgb[0]}] diff --git a/fpga/src/alu.vhd b/fpga/src/alu.vhd index 35e1808..5f791b6 100644 --- a/fpga/src/alu.vhd +++ b/fpga/src/alu.vhd @@ -24,40 +24,64 @@ end alu; -- Architecture implementation of alu: implements table architecture implementation of alu is - + signal buffer_out : std_logic_vector(7 downto 0) := (others => '0'); begin -- Process p_instruction - p_instruction : process (instruction) -- runs only, when instruction changed + p_instruction : process (extern_in, instruction, old_cell, old_pointer) begin case instruction is when "000" => enable_cell <= '0'; enable_ptr <= '1'; new_pointer <= std_logic_vector(unsigned(old_pointer) + 1); + + new_cell <= old_cell; + buffer_out <= "00000000"; when "001" => enable_cell <= '0'; enable_ptr <= '1'; new_pointer <= std_logic_vector(unsigned(old_pointer) - 1); + + new_cell <= old_cell; + buffer_out <= "00000000"; when "010" => enable_cell <= '1'; enable_ptr <= '0'; new_cell <= std_logic_vector(unsigned(old_cell) + 1); + + new_pointer <= old_pointer; + buffer_out <= "00000000"; when "011" => enable_cell <= '1'; enable_ptr <= '0'; new_cell <= std_logic_vector(unsigned(old_cell) - 1); + + new_pointer <= old_pointer; + buffer_out <= "00000000"; when "100" => enable_cell <= '1'; enable_ptr <= '0'; new_cell <= extern_in; + + new_pointer <= old_pointer; + buffer_out <= "00000000"; when "101" => enable_cell <= '0'; enable_ptr <= '0'; - extern_out <= old_cell; + buffer_out <= old_cell; + + new_pointer <= old_pointer; + new_cell <= old_cell; when others => enable_cell <= '0'; enable_ptr <= '0'; + + new_pointer <= old_pointer; + new_cell <= old_cell; + buffer_out <= "00000000"; end case; end process; + extern_out <= buffer_out; + end implementation; diff --git a/fpga/src/bfpu.vhd b/fpga/src/bfpu.vhd index ff6d86c..ce188a0 100644 --- a/fpga/src/bfpu.vhd +++ b/fpga/src/bfpu.vhd @@ -11,6 +11,7 @@ entity bfpu is port( clk : in std_logic; -- board clock sw : in std_logic_vector(7 downto 0); -- Input for instruction , + debug : out std_logic_vector(7 downto 0); -- Value of currently selected logic cell. led : out std_logic_vector(7 downto 0) -- Output for instruction . ); end bfpu; @@ -169,5 +170,6 @@ begin s_enable_ptr <= s_skip and s_enable_ptr_o; s_enable_cells <= s_skip and s_enable_cells_o; + debug <= s_cell_out; end arch; diff --git a/fpga/src/branch.vhd b/fpga/src/branch.vhd index cf7c1c7..cafd8d8 100644 --- a/fpga/src/branch.vhd +++ b/fpga/src/branch.vhd @@ -6,6 +6,8 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; +-- TODO: CHECK PUSH AND POP AND THE PHASES/STATES OF PC_ENABLE + -- Entity branch: branch entity branch is port( @@ -29,88 +31,68 @@ architecture impl of branch is signal nested : std_logic_vector(7 downto 0) := (others => '0'); -- count nested loops signal skip_internal : std_logic := '0'; signal stack_ptr : std_logic_vector(7 downto 0) := (others => '0'); - signal push_state : std_logic := '1'; begin - -- Process p_skip: set skip to true - p_skip : process (clk) + -- Process p_branch: set skip to true + p_branch : process (clk, skip_internal, instruction, cell_value) begin if rising_edge(clk) then if instruction = "110" and unsigned(cell_value) = 0 and unsigned(nested) = 0 and skip_internal = '0' then skip_internal <= '1'; end if; end if; - end process; - -- Process p_continue: set skip to false - p_continue : process (clk) - begin + -- set skip to false if rising_edge(clk) then if instruction = "111" and unsigned(nested) = 0 and skip_internal = '1' then skip_internal <= '0'; end if; end if; - end process; - -- Process p_nest : raise nest by one as [ is passed - p_nest : process (clk) - begin + -- Process p_nest : raise nest by one as [ is passed if rising_edge(clk) then if instruction = "110" and skip_internal = '1' then nested <= std_logic_vector(unsigned(nested) + 1); end if; end if; - end process; - -- Process p_unnest : lower nest, as ] is passed - p_unnest : process (clk) - begin + -- Process p_unnest : lower nest, as ] is passed if rising_edge(clk) then if instruction = "111" and unsigned(nested) > 0 and skip_internal = '1' then nested <= std_logic_vector(unsigned(nested) - 1); end if; end if; - end process; - -- Process p_push : raise stack and push address - p_push : process (clk) - begin + -- Process p_push : raise stack and push address if rising_edge(clk) and instruction = "110" and unsigned(cell_value) > 0 and skip_internal = '0' then - if push_state = '0' then + if pc_enable = '0' then -- restore push_state and push address addr_stack(to_integer(unsigned(stack_ptr))) <= instr_addr; - push_state <= '1'; pc_enable <= '1'; else -- raise stack, disable pc and unset push_state stack_ptr <= std_logic_vector(unsigned(stack_ptr) + 1); pc_enable <= '0'; - push_state <= '0'; end if; end if; - end process; - -- Process p_pop : read address to jump address and lower stack - p_pop : process (clk) - begin + -- Process p_pop : read address to jump address and lower stack if rising_edge(clk) and instruction = "111" and unsigned(cell_value) > 0 and skip_internal = '0' then - if push_state = '1' then + if pc_enable = '0' then -- set address to pc_out, disable pc and unset push_state pc_out <= addr_stack(to_integer(unsigned(stack_ptr))); - pc_enable <= '0'; - push_state <= '0'; + pc_enable <= '1'; else -- set pc to enabled, restore push_state and lower stack - pc_enable <= '1'; - push_state <= '1'; + pc_enable <= '0'; stack_ptr <= std_logic_vector(unsigned(stack_ptr) - 1); end if; end if; -- regulate jump if rising_edge(clk) then - if instruction = "111" and unsigned(cell_value) > 0 and skip_internal = '0' and push_state = '0' then + if instruction = "111" and unsigned(cell_value) > 0 and skip_internal = '0' and pc_enable = '1' then jump <= '1'; else jump <= '0'; diff --git a/fpga/src/cellMemory.vhd b/fpga/src/cellMemory.vhd index b7da2d6..4ce7488 100644 --- a/fpga/src/cellMemory.vhd +++ b/fpga/src/cellMemory.vhd @@ -28,7 +28,7 @@ architecture arch of cellblock is begin -- Process clk_read - clk_read : process (clk) -- runs only, when clk changed + clk_read : process (clk, enable) -- runs only, when clk changed begin if rising_edge(clk) and enable = '1' then diff --git a/fpga/src/instructionMemory.vhd b/fpga/src/instructionMemory.vhd index aa9c6c7..b30f97d 100644 --- a/fpga/src/instructionMemory.vhd +++ b/fpga/src/instructionMemory.vhd @@ -19,9 +19,10 @@ end instructionMemory; -- Architecture arch of instructionMemory: read on every clock cycle to instruction. architecture arch of instructionMemory is + type imem is array(0 to 255) of std_logic_vector(2 downto 0); - - signal memory : imem := (b"000", b"001", b"010", b"011", b"100", b"101", b"110", b"111", others => "000"); + -- [+.] + signal memory : imem := (b"110", b"010", b"101", b"111", others => "000"); begin -- Process clk_read clk_read : process (clk) -- runs only, when clk changed diff --git a/fpga/src/memoryPointer.vhd b/fpga/src/memoryPointer.vhd index 141395b..857afa6 100644 --- a/fpga/src/memoryPointer.vhd +++ b/fpga/src/memoryPointer.vhd @@ -23,7 +23,7 @@ architecture implement_ptr of ptr is begin -- Process Write set new_ptr - write : process (clk) -- runs only, when clk changed + write : process (clk, enable_ptr) -- runs only, when clk changed begin if rising_edge(clk) and enable_ptr = '1' then reg <= new_ptr; diff --git a/fpga/src/programCounter.vhd b/fpga/src/programCounter.vhd index 5846e07..22e1d69 100644 --- a/fpga/src/programCounter.vhd +++ b/fpga/src/programCounter.vhd @@ -23,7 +23,7 @@ architecture pc of program_counter is begin -- Process count - count : process (clk, enable, jmp) -- runs only, when clk, enable, jmp changed + count : process (clk, enable) -- runs only, when clk, enable, jmp changed begin if rising_edge(clk) and enable = '1' then if jmp = '1' then