Init TinyTapeout repository

TinyTapeout/LICENSE

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TinyTapeout/README.md

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+# Buszustände
+
+## Nachrichtenaufbau
+
+5 Bit für 21 Zustände:
+
+|Bit(s)|Description |
+|------|------------|
+|0     |Start Symbol|
+|1-8   |Address     |
+|9     |Read/Write  |
+|10    |Acknoledge  |
+|11-18 |Data        |
+|19    |Acknoledge  |
+|20    |Stop Symbol |
+
+---------------------------------
+
+## Zustände
+
+- Idle
+- sende Start
+- sende Adresse
+- sende Nachrichtenrichtung
+- sende Acknowledge
+- sende Datenbyte
+- sende Acknowledge
+- sende Stop
+- Idle
+
+![Zustandsautomat](./States.png "NOT FOUND!")
+
+---------------------------------

TinyTapeout/info.yaml

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+--- 
+# TinyTapeout project information
+project:
+  wokwi_id:    0        # If using wokwi, set this to your project's ID
+
+# If using an HDL, set wokwi_id as 0 and uncomment and list your source files here. 
+# Source files must be in ./src and you must list each source file separately
+  source_files:        
+    - bfpu.v
+#    - decoder.v
+  top_module:  "tt_um_yannickreiss_bfpu"      # Put the name of your top module here, must start with "tt_um_". Make it unique by including your github username
+
+# How many tiles your design occupies? A single tile is about 167x108 uM.
+  tiles: "1x1"    # Valid values: 1x1, 1x2, 2x2, 4x2 or 8x2
+
+# Keep a track of the submission yaml
+yaml_version: 4
+
+# As everyone will have access to all designs, try to make it easy for someone new to your design to know what
+# it does and how to operate it. This info will be automatically collected and used to make a datasheet for the chip.
+#
+# Here is a great example: https://github.com/davidsiaw/tt02-davidsiaw-stackcalc/blob/38c5647f83aad2aec675d566aa3d67b98f0aac81/info.yaml
+documentation: 
+  author:       "Yannick Reiß"      # Your name
+  title:        "Brainfuck processing unit"      # Project title
+  language:     "Verilog" # other examples include Verilog, Amaranth, VHDL, etc
+  description:  "MPU to process brainfuck instructions."      # Short description of what your project does
+
+# Longer description of how the project works. You can use standard markdown format.
+  how_it_works: |
+      Please refer to the README.md for additional information and where to find it.
+
+# Instructions on how someone could test your project, include things like what buttons do what and how to set the clock if needed
+  how_to_test:  |
+      The processing unit takes and prints a byte using the unidirectional pins when triggered by an instruction.
+      The instruction memory is controlled with a serial bus on the bidirectional pins.
+      
+      Please refer to the README.md for further information.
+
+# A description of what the inputs do (e.g. red button, SPI CLK, SPI MOSI, etc).
+  inputs:               
+    - read lsb
+    - read
+    - read
+    - read
+    - read
+    - read
+    - read
+    - read msb
+# A description of what the outputs do (e.g. status LED, SPI MISO, etc)
+  outputs:
+    - write lsb
+    - write
+    - write
+    - write
+    - write
+    - write
+    - write
+    - write msb
+# A description of what the bidirectional I/O pins do (e.g. I2C SDA, I2C SCL, etc)
+  bidirectional:
+    - instruction bus lsb
+    - instruction bus
+    - instruction bus
+    - instruction bus
+    - instruction bus
+    - instruction bus
+    - instruction bus
+    - instruction bus msb
+
+# The following fields are optional
+  tag:          "microprocessor"      # comma separated list of tags: test, encryption, experiment, clock, animation, utility, industrial, pwm, fpga, alu, microprocessor, risc, riscv, sensor, signal generator, fft, filter, music, bcd, sound, serial, timer, random number generator, calculator, decoder, counter, puzzle, multiplier, game, oscillator,
+  external_hw:  "some pc to run the compiler, something to connect the input, output and bus for programming."      # Describe any external hardware needed
+  discord:      "schnick_"      # Your discord handle, used for communication and automatically assigning tapeout role after a submission
+  doc_link:     "https://gitlab.schnick.duckdns.org/schnick/bfpu"      # URL to longer form documentation, eg the README.md in your repository
+  clock_hz:     0       # Clock frequency in Hz (if required)
+  picture:      ""      # relative path to a picture in your repository

TinyTapeout/src/bfpu.v

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+module tt_um_yannickreiss_bfpu(input wire [7:0] ui_in,    // Dedicated inputs
+                                     output wire [7:0] uo_out,  // Dedicated outputs
+                                     input wire [7:0] uio_in,   // IOs: Input path
+                                     output wire [7:0] uio_out, // IOs: Output path
+                                     output wire [7:0] uio_oe,  // IOs: Enable path (active high: 0 = input, 1 = output
+                                     input wire ena,
+                                     input wire clk,
+                                     input wire rst_n);
+
+
+
+endmodule

TinyTapeout/src/cells.v

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+/*
+ This file provides the mapping from the Wokwi modules to Verilog HDL
+ 
+ It's only needed for Wokwi designs
+ 
+ */
+`define default_netname none
+
+// custom cells
+module reg_cell (input wire clk,
+                 input wire d,
+                 output wire q);
+    reg register;
+    
+    always @(posedge clk) begin
+        register = d;
+    end
+    
+    assign q = register;
+endmodule // reg_cell
+    
+    // TinyTapeout cells
+    module buffer_cell (
+        input wire in,
+        output wire out
+        );
+        assign out = in;
+    endmodule
+        
+        module and_cell (
+            input wire a,
+            input wire b,
+            output wire out
+            );
+            
+            assign out = a & b;
+        endmodule
+            
+            module or_cell (
+                input wire a,
+                input wire b,
+                output wire out
+                );
+                
+                assign out = a | b;
+            endmodule
+                
+                module xor_cell (
+                    input wire a,
+                    input wire b,
+                    output wire out
+                    );
+                    
+                    assign out = a ^ b;
+                endmodule
+                    
+                    module nand_cell (
+                        input wire a,
+                        input wire b,
+                        output wire out
+                        );
+                        
+                        assign out = !(a&b);
+                    endmodule
+                        
+                        module not_cell (
+                            input wire in,
+                            output wire out
+                            );
+                            
+                            assign out = !in;
+                        endmodule
+                            
+                            module mux_cell (
+                                input wire a,
+                                input wire b,
+                                input wire sel,
+                                output wire out
+                                );
+                                
+                                assign out = sel ? b : a;
+                            endmodule
+                                
+                                module dff_cell (
+                                    input wire clk,
+                                    input wire d,
+                                    output reg q,
+                                    output wire notq
+                                    );
+                                    
+                                    assign notq = !q;
+                                    always @(posedge clk)
+                                        q <= d;
+                                    
+                                endmodule
+                                    
+                                    module dffsr_cell (
+                                        input wire clk,
+                                        input wire d,
+                                        input wire s,
+                                        input wire r,
+                                        output reg q,
+                                        output wire notq
+                                        );
+                                        
+                                        assign notq = !q;
+                                        
+                                        always @(posedge clk or posedge s or posedge r) begin
+                                            if (r)
+                                                q <= 0;
+                                            else if (s)
+                                                q <= 1;
+                                            else
+                                                q <= d;
+                                        end
+                                    endmodule

TinyTapeout/src/config.tcl

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+# PLEASE DO NOT EDIT THIS FILE!
+# If you get stuck with this config, please open an issue or get in touch via the discord.
+
+# Configuration docs: https://openlane.readthedocs.io/en/latest/reference/configuration.html
+
+# User config
+set script_dir [file dirname [file normalize [info script]]]
+
+# read some user config that is written by the setup.py program.
+# - the name of the module is defined
+# - the list of source files
+source $::env(DESIGN_DIR)/user_config.tcl
+
+# save some time
+set ::env(RUN_KLAYOUT_XOR) 0
+set ::env(RUN_KLAYOUT_DRC) 0
+
+# don't put clock buffers on the outputs
+set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
+
+# allow use of specific sky130 cells
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+
+# reduce wasted space
+set ::env(TOP_MARGIN_MULT) 1
+set ::env(BOTTOM_MARGIN_MULT) 1
+set ::env(LEFT_MARGIN_MULT) 6
+set ::env(RIGHT_MARGIN_MULT) 6
+
+# absolute die size
+set ::env(FP_SIZING) absolute
+
+set ::env(PL_BASIC_PLACEMENT) {0}
+set ::env(GRT_ALLOW_CONGESTION) "1"
+
+# otherwise fails on small designs at global placement
+set ::env(GRT_CELL_PADDING) "4"
+
+set ::env(FP_IO_HLENGTH) 2
+set ::env(FP_IO_VLENGTH) 2
+
+# use alternative efabless decap cells to solve LI density issue
+set ::env(DECAP_CELL) "\
+    sky130_fd_sc_hd__decap_3 \
+    sky130_fd_sc_hd__decap_4 \
+    sky130_fd_sc_hd__decap_6 \
+    sky130_fd_sc_hd__decap_8 \
+    sky130_ef_sc_hd__decap_12"
+
+# clock
+set ::env(CLOCK_TREE_SYNTH) 1
+# period is in ns, so 20ns == 50mHz
+set ::env(CLOCK_PERIOD) "20"
+set ::env(CLOCK_PORT) {clk}
+
+# hold/slack margin
+# set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) 0.8 
+# set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) 0.8 
+
+# don't use power rings or met5
+set ::env(DESIGN_IS_CORE) 0
+set ::env(RT_MAX_LAYER) {met4}