diff --git a/bfpcompiler/.Xil/Vivado-33785-lilith/elab.rtd b/bfpcompiler/.Xil/Vivado-33785-lilith/elab.rtd new file mode 100644 index 0000000..c24923d Binary files /dev/null and b/bfpcompiler/.Xil/Vivado-33785-lilith/elab.rtd differ diff --git a/bfpcompiler/.Xil/Vivado-33785-lilith/realtime/bfpu.tcl b/bfpcompiler/.Xil/Vivado-33785-lilith/realtime/bfpu.tcl new file mode 100644 index 0000000..ad3e883 --- /dev/null +++ b/bfpcompiler/.Xil/Vivado-33785-lilith/realtime/bfpu.tcl @@ -0,0 +1,114 @@ +# +# Synthesis run script generated by Vivado +# + +namespace eval rt { + variable rc +} +set rt::rc [catch { + uplevel #0 { + set ::env(BUILTIN_SYNTH) true + source $::env(HRT_TCL_PATH)/rtSynthPrep.tcl + rt::HARTNDb_resetJobStats + rt::HARTNDb_resetSystemStats + rt::HARTNDb_startSystemStats + rt::HARTNDb_startJobStats + set rt::cmdEcho 0 + rt::set_parameter writeXmsg true + rt::set_parameter enableParallelHelperSpawn true + set ::env(RT_TMP) "./.Xil/Vivado-33785-lilith/realtime/tmp" + if { [ info exists ::env(RT_TMP) ] } { + file delete -force $::env(RT_TMP) + file mkdir $::env(RT_TMP) + } + + rt::delete_design + + rt::set_parameter datapathDensePacking false + set rt::partid xc7a100tcsg324-1 + file delete -force synth_hints.os + + set rt::multiChipSynthesisFlow false + set rt::enableVHDL2008 1 + source $::env(SYNTH_COMMON)/common.tcl + set rt::defaultWorkLibName xil_defaultlib + + set rt::useElabCache false + if {$rt::useElabCache == false} { + rt::read_vhdl -lib xil_defaultlib { + /home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/programCounter.vhd + /home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/bfpu.vhd + } + rt::read_vhdl -vhdl2008 -lib xil_defaultlib { + /home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/alu.vhd + /home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/branch.vhd + /home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/cellMemory.vhd + /home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/instructionMemory.vhd + /home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/memoryPointer.vhd + } + rt::filesetChecksum + } + rt::set_parameter usePostFindUniquification false + set rt::top bfpu + rt::set_parameter enableIncremental true + rt::set_parameter markDebugPreservationLevel "enable" + set rt::reportTiming false + rt::set_parameter elaborateOnly true + rt::set_parameter elaborateRtl true + rt::set_parameter eliminateRedundantBitOperator false + rt::set_parameter dataflowBusHighlighting false + rt::set_parameter generateDataflowBusNetlist false + rt::set_parameter dataFlowViewInElab false + rt::set_parameter busViewFixBrokenConnections false + rt::set_parameter elaborateRtlOnlyFlow true + rt::set_parameter writeBlackboxInterface true + rt::set_parameter merge_flipflops true + rt::set_parameter srlDepthThreshold 3 + rt::set_parameter rstSrlDepthThreshold 4 +# MODE: + rt::set_parameter webTalkPath {} + rt::set_parameter synthDebugLog false + rt::set_parameter printModuleName false + rt::set_parameter enableSplitFlowPath "./.Xil/Vivado-33785-lilith/" + set ok_to_delete_rt_tmp true + if { [rt::get_parameter parallelDebug] } { + set ok_to_delete_rt_tmp false + } + if {$rt::useElabCache == false} { + set oldMIITMVal [rt::get_parameter maxInputIncreaseToMerge]; rt::set_parameter maxInputIncreaseToMerge 1000 + set oldCDPCRL [rt::get_parameter createDfgPartConstrRecurLimit]; rt::set_parameter createDfgPartConstrRecurLimit 1 + $rt::db readXRFFile + rt::run_rtlelab -module $rt::top + rt::set_parameter maxInputIncreaseToMerge $oldMIITMVal + rt::set_parameter createDfgPartConstrRecurLimit $oldCDPCRL + } + + set rt::flowresult [ source $::env(SYNTH_COMMON)/flow.tcl ] + rt::HARTNDb_stopJobStats + if { $rt::flowresult == 1 } { return -code error } + + + set hsKey [rt::get_parameter helper_shm_key] + if { $hsKey != "" && [info exists ::env(BUILTIN_SYNTH)] && [rt::get_parameter enableParallelHelperSpawn] } { + $rt::db killSynthHelper $hsKey + } + rt::set_parameter helper_shm_key "" + if { [ info exists ::env(RT_TMP) ] } { + if { [info exists ok_to_delete_rt_tmp] && $ok_to_delete_rt_tmp } { + file delete -force $::env(RT_TMP) + } + } + + source $::env(HRT_TCL_PATH)/rtSynthCleanup.tcl + } ; #end uplevel +} rt::result] + +if { $rt::rc } { + $rt::db resetHdlParse + set hsKey [rt::get_parameter helper_shm_key] + if { $hsKey != "" && [info exists ::env(BUILTIN_SYNTH)] && [rt::get_parameter enableParallelHelperSpawn] } { + $rt::db killSynthHelper $hsKey + } + source $::env(HRT_TCL_PATH)/rtSynthCleanup.tcl + return -code "error" $rt::result +} diff --git a/bfpcompiler/.Xil/Vivado-33785-lilith/realtime/dupFiles.rpt b/bfpcompiler/.Xil/Vivado-33785-lilith/realtime/dupFiles.rpt new file mode 100644 index 0000000..abb94af --- /dev/null +++ b/bfpcompiler/.Xil/Vivado-33785-lilith/realtime/dupFiles.rpt @@ -0,0 +1 @@ +CRC performance measure: elapsed=00:00:00s;;memory_peak=8164.695MB;;memory_gain=0.000MB diff --git a/bfpcompiler/long_run.bin b/bfpcompiler/long_run.bin new file mode 100644 index 0000000..fcba3b8 --- /dev/null +++ b/bfpcompiler/long_run.bin @@ -0,0 +1 @@ +(b"010",b"110",b"000",b"011",b"110",b"101",b"011",b"000",b"011",b"110",b"011",b"000",b"011",b"110",b"011",b"000",b"011",b"110",b"011",b"111",b"001",b"111",b"001",b"111",b"001",b"111",b"001",b"111",(others=>'0')); \ No newline at end of file diff --git a/bfpcompiler/src/assembling.c b/bfpcompiler/src/assembling.c index 192284f..2f7d9b5 100644 --- a/bfpcompiler/src/assembling.c +++ b/bfpcompiler/src/assembling.c @@ -95,7 +95,6 @@ static char* intoVHDL (char* tokens) { } /* This is the closing term. */ - binary[pos++] = '('; binary[pos++] = 'o'; binary[pos++] = 't'; binary[pos++] = 'h'; @@ -104,10 +103,11 @@ static char* intoVHDL (char* tokens) { binary[pos++] = 's'; binary[pos++] = '='; binary[pos++] = '>'; - binary[pos++] = '\''; + binary[pos++] = '"'; binary[pos++] = '0'; - binary[pos++] = '\''; - binary[pos++] = ')'; + binary[pos++] = '0'; + binary[pos++] = '0'; + binary[pos++] = '"'; /* Close initial memory. */ binary[pos++] = ')'; diff --git a/bfpcompiler/vivado.jou b/bfpcompiler/vivado.jou new file mode 100644 index 0000000..036f98f --- /dev/null +++ b/bfpcompiler/vivado.jou @@ -0,0 +1,34 @@ +#----------------------------------------------------------- +# Vivado v2023.1 (64-bit) +# SW Build 3865809 on Sun May 7 15:04:56 MDT 2023 +# IP Build 3864474 on Sun May 7 20:36:21 MDT 2023 +# SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023 +# Start of session at: Thu Oct 5 15:20:21 2023 +# Process ID: 33785 +# Current directory: /home/nick/Documents/Programming/Brainfuck/BPFU/bfpcompiler +# Command line: vivado +# Log file: /home/nick/Documents/Programming/Brainfuck/BPFU/bfpcompiler/vivado.log +# Journal file: /home/nick/Documents/Programming/Brainfuck/BPFU/bfpcompiler/vivado.jou +# Running On: lilith, OS: Linux, CPU Frequency: 1687.184 MHz, CPU Physical cores: 4, Host memory: 8201 MB +#----------------------------------------------------------- +start_gui +open_project /home/nick/brainfuck/brainfuck.xpr +update_compile_order -fileset sources_1 +reset_run synth_1 +launch_runs impl_1 -to_step write_bitstream -jobs 4 +wait_on_run impl_1 +reset_run synth_1 +launch_runs synth_1 -jobs 4 +wait_on_run synth_1 +reset_run synth_1 +launch_runs impl_1 -to_step write_bitstream -jobs 4 +wait_on_run impl_1 +reset_run synth_1 +launch_runs synth_1 -jobs 4 +wait_on_run synth_1 +reset_run synth_1 +launch_runs synth_1 -jobs 4 +wait_on_run synth_1 +synth_design -rtl -rtl_skip_mlo -name rtl_1 +launch_runs impl_1 -jobs 4 +wait_on_run impl_1 diff --git a/bfpcompiler/vivado.log b/bfpcompiler/vivado.log new file mode 100644 index 0000000..7f2ae40 --- /dev/null +++ b/bfpcompiler/vivado.log @@ -0,0 +1,171 @@ +#----------------------------------------------------------- +# Vivado v2023.1 (64-bit) +# SW Build 3865809 on Sun May 7 15:04:56 MDT 2023 +# IP Build 3864474 on Sun May 7 20:36:21 MDT 2023 +# SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023 +# Start of session at: Thu Oct 5 15:20:21 2023 +# Process ID: 33785 +# Current directory: /home/nick/Documents/Programming/Brainfuck/BPFU/bfpcompiler +# Command line: vivado +# Log file: /home/nick/Documents/Programming/Brainfuck/BPFU/bfpcompiler/vivado.log +# Journal file: /home/nick/Documents/Programming/Brainfuck/BPFU/bfpcompiler/vivado.jou +# Running On: lilith, OS: Linux, CPU Frequency: 1687.184 MHz, CPU Physical cores: 4, Host memory: 8201 MB +#----------------------------------------------------------- +start_gui +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc707:part0:1.4 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc707/1.4/board.xml as part xc7vx485tffg1761-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc709:part0:1.8 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc709/1.8/board.xml as part xc7vx690tffg1761-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:2.2 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/2.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:3.0 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/3.0/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:3.1 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/3.1/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:3.2 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/3.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_newl:part0:1.0 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190_newl/production/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_newl:part0:1.1 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190_newl/production/1.1/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.1 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.1/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.0 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.0/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.1 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.1/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_mpsoc:part0:1.0 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml as part xczu19eg-ffvd1760-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_rfsoc:part0:1.0 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml as part xczu21dr-ffvd1156-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158:part0:1.0 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/production/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.1 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.1/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.0 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.0/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.1 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.1/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.2 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_newl:part0:1.0 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180_newl/production/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_newl:part0:1.1 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180_newl/production/1.1/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120:part0:1.0 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/production/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120:part0:1.1 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/production/1.1/board.xml as part xcvp1202-vsva2785-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.3 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.3/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.1 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.1/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180:part0:1.0 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/production/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180:part0:1.1 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/production/1.1/board.xml as part xcvp1802-lsvc4072-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.1 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.1/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.4 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc706/1.4/board.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.3 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.3/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.4 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.4/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.2 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.2/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.3 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.3/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.4 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.4/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1275:part0:1.0 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1275/1.0/board.xml as part xczu29dr-ffvf1760-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1285:part0:1.0 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1285/1.0/board.xml as part xczu39dr-ffvf1760-2-i specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208:part0:2.0 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/production/2.0/board.xml as part xczu48dr-fsvg1517-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216:part0:2.0 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/production/2.0/board.xml as part xczu49dr-ffvf1760-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available +open_project /home/nick/brainfuck/brainfuck.xpr +INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory '/home/nick/brainfuck/brainfuck.gen/sources_1'. +Scanning sources... +Finished scanning sources +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/ip'. +open_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:08 . Memory (MB): peak = 7702.613 ; gain = 228.406 ; free physical = 667 ; free virtual = 12643 +update_compile_order -fileset sources_1 +reset_run synth_1 +INFO: [Project 1-1161] Replacing file /home/nick/brainfuck/brainfuck.srcs/utils_1/imports/synth_1/bfpu.dcp with file /home/nick/brainfuck/brainfuck.runs/synth_1/bfpu.dcp +launch_runs impl_1 -to_step write_bitstream -jobs 4 +[Thu Oct 5 15:23:43 2023] Launched synth_1... +Run output will be captured here: /home/nick/brainfuck/brainfuck.runs/synth_1/runme.log +[Thu Oct 5 15:23:43 2023] Launched impl_1... +Run output will be captured here: /home/nick/brainfuck/brainfuck.runs/impl_1/runme.log +reset_run synth_1 +launch_runs synth_1 -jobs 4 +[Thu Oct 5 15:27:31 2023] Launched synth_1... +Run output will be captured here: /home/nick/brainfuck/brainfuck.runs/synth_1/runme.log +reset_run synth_1 +launch_runs impl_1 -to_step write_bitstream -jobs 4 +[Thu Oct 5 15:34:29 2023] Launched synth_1... +Run output will be captured here: /home/nick/brainfuck/brainfuck.runs/synth_1/runme.log +[Thu Oct 5 15:34:29 2023] Launched impl_1... +Run output will be captured here: /home/nick/brainfuck/brainfuck.runs/impl_1/runme.log +reset_run synth_1 +launch_runs synth_1 -jobs 4 +[Thu Oct 5 15:38:03 2023] Launched synth_1... +Run output will be captured here: /home/nick/brainfuck/brainfuck.runs/synth_1/runme.log +reset_run synth_1 +launch_runs synth_1 -jobs 4 +[Thu Oct 5 15:38:50 2023] Launched synth_1... +Run output will be captured here: /home/nick/brainfuck/brainfuck.runs/synth_1/runme.log +synth_design -rtl -rtl_skip_mlo -name rtl_1 +Command: synth_design -rtl -rtl_skip_mlo -name rtl_1 +Starting synth_design +Using part: xc7a100tcsg324-1 +Top: bfpu +INFO: [Device 21-403] Loading part xc7a100tcsg324-1 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 8538.523 ; gain = 373.828 ; free physical = 593 ; free virtual = 10906 +--------------------------------------------------------------------------------- +WARNING: [Synth 8-9112] actual for formal port 'enable' is neither a static name nor a globally static expression [/home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/bfpu.vhd:179] +INFO: [Synth 8-638] synthesizing module 'bfpu' [/home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/bfpu.vhd:20] +INFO: [Synth 8-3491] module 'instructionMemory' declared at '/home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/instructionMemory.vhd:10' bound to instance 'instrMemory' of component 'instructionMemory' [/home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/bfpu.vhd:139] +INFO: [Synth 8-638] synthesizing module 'instructionMemory' [/home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/instructionMemory.vhd:20] +INFO: [Synth 8-256] done synthesizing module 'instructionMemory' (0#1) [/home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/instructionMemory.vhd:20] +INFO: [Synth 8-3491] module 'alu' declared at '/home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/alu.vhd:10' bound to instance 'alu_entity' of component 'alu' [/home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/bfpu.vhd:145] +INFO: [Synth 8-638] synthesizing module 'alu' [/home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/alu.vhd:26] +INFO: [Synth 8-256] done synthesizing module 'alu' (0#1) [/home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/alu.vhd:26] +INFO: [Synth 8-3491] module 'ptr' declared at '/home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/memoryPointer.vhd:10' bound to instance 'ptr_bf' of component 'ptr' [/home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/bfpu.vhd:159] +INFO: [Synth 8-638] synthesizing module 'ptr' [/home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/memoryPointer.vhd:21] +INFO: [Synth 8-256] done synthesizing module 'ptr' (0#1) [/home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/memoryPointer.vhd:21] +INFO: [Synth 8-3491] module 'cellblock' declared at '/home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/cellMemory.vhd:11' bound to instance 'cellblock_bf' of component 'cellblock' [/home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/bfpu.vhd:167] +INFO: [Synth 8-638] synthesizing module 'cellblock' [/home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/cellMemory.vhd:24] +INFO: [Synth 8-256] done synthesizing module 'cellblock' (0#1) [/home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/cellMemory.vhd:24] +INFO: [Synth 8-3491] module 'program_counter' declared at '/home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/programCounter.vhd:10' bound to instance 'pc' of component 'program_counter' [/home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/bfpu.vhd:176] +INFO: [Synth 8-638] synthesizing module 'program_counter' [/home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/programCounter.vhd:21] +INFO: [Synth 8-256] done synthesizing module 'program_counter' (0#1) [/home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/programCounter.vhd:21] +INFO: [Synth 8-3491] module 'branch' declared at '/home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/branch.vhd:12' bound to instance 'branch_bf' of component 'branch' [/home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/bfpu.vhd:185] +INFO: [Synth 8-638] synthesizing module 'branch' [/home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/branch.vhd:28] +INFO: [Synth 8-256] done synthesizing module 'branch' (0#1) [/home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/branch.vhd:28] +INFO: [Synth 8-256] done synthesizing module 'bfpu' (0#1) [/home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/bfpu.vhd:20] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 8640.492 ; gain = 475.797 ; free physical = 485 ; free virtual = 10803 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 8655.336 ; gain = 490.641 ; free physical = 471 ; free virtual = 10790 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 8655.336 ; gain = 490.641 ; free physical = 471 ; free virtual = 10790 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 8655.336 ; gain = 0.000 ; free physical = 471 ; free virtual = 10790 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/nick/Documents/Programming/Brainfuck/BPFU/fpga/constrainits.xdc] +Finished Parsing XDC File [/home/nick/Documents/Programming/Brainfuck/BPFU/fpga/constrainits.xdc] +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 8730.094 ; gain = 0.000 ; free physical = 444 ; free virtual = 10768 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +RTL Elaboration Complete: : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 8831.926 ; gain = 667.230 ; free physical = 344 ; free virtual = 10682 +23 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 8831.926 ; gain = 962.332 ; free physical = 344 ; free virtual = 10682 +INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] +INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] +launch_runs impl_1 -jobs 4 +[Thu Oct 5 15:40:25 2023] Launched impl_1... +Run output will be captured here: /home/nick/brainfuck/brainfuck.runs/impl_1/runme.log diff --git a/bfpcompiler/vivado_pid33785.str b/bfpcompiler/vivado_pid33785.str new file mode 100644 index 0000000..fe3220c --- /dev/null +++ b/bfpcompiler/vivado_pid33785.str @@ -0,0 +1,467 @@ +/* + +AMD Vivado v2023.1 (64-bit) [Major: 2023, Minor: 1] +SW Build: 3865809 on Sun May 7 15:04:56 MDT 2023 +IP Build: 3864474 on Sun May 7 20:36:21 MDT 2023 +IP Build: 3864474 on Sun May 7 20:36:21 MDT 2023 + +Process ID (PID): 33785 +License: Customer +Mode: GUI Mode + +Current time: Thu Oct 05 15:21:14 CEST 2023 +Time zone: Central European Standard Time (Europe/Berlin) + +OS: DISTRIB_ID="EndeavourOS" +OS Version: 6.5.5-arch1-1 +OS Architecture: amd64 +Available processors (cores): 4 + +Display: 0 +Screen size: 1920x1080 +Screen resolution (DPI): 100 +Available screens: 2 +Default font: family=Dialog,name=Dialog,style=plain,size=12 +Scale size: 12 +OS font scaling: 100% + +Java version: 17.0.3 64-bit +JavaFX version: 17.0.1 +Java home: /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/tps/lnx64/jre17.0.3_7 +Java executable: /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/tps/lnx64/jre17.0.3_7/bin/java +Java arguments: [-Dsun.java2d.pmoffscreen=false, -Dhttps.protocols=TLSv1,TLSv1.1,TLSv1.2, -Dsun.java2d.xrender=false, -Djdk.gtk.version=2, -Dsun.java2d.uiScale.enabled=false, -Dswing.aatext=true, -XX:-UsePerfData, -Djdk.map.althashing.threshold=512, -XX:StringTableSize=4072, -XX:+UseStringDeduplication, -XX:MaxGCPauseMillis=200, -XX:+ParallelRefProcEnabled, --add-opens=java.desktop/javax.swing.plaf.synth=ALL-UNNAMED, --add-opens=java.base/java.nio=ALL-UNNAMED, --add-opens=java.desktop/sun.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.tree=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.basic=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.synth=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.basic=ALL-UNNAMED, --add-opens=java.desktop/javax.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.tree=ALL-UNNAMED, --add-opens=java.desktop/java.awt.event=ALL-UNNAMED, --add-exports=java.desktop/javax.swing.plaf.synth=ALL-UNNAMED, --add-exports=java.base/java.nio=ALL-UNNAMED, --add-exports=java.desktop/sun.swing=ALL-UNNAMED, --add-exports=java.desktop/javax.swing=ALL-UNNAMED, --add-exports=java.desktop/javax.swing.tree=ALL-UNNAMED, --add-exports=java.desktop/javax.swing.plaf.basic=ALL-UNNAMED, --add-exports=java.desktop/sun.swing=ALL-UNNAMED, --add-exports=java.desktop/sun.swing.table=ALL-UNNAMED, --add-exports=java.desktop/sun.swing.plaf.synth=ALL-UNNAMED, --add-exports=java.desktop/sun.awt.shell=ALL-UNNAMED, --add-exports=java.base/sun.security.action=ALL-UNNAMED, --add-exports=java.desktop/sun.font=ALL-UNNAMED, --add-opens=java.desktop/sun.awt.X11=ALL-UNNAMED, -XX:NewSize=80m, -XX:MaxNewSize=80m, -Xms512m, -Xmx4072m, -Xss10m, -Xrs] +Java initial memory (-Xms): 512 MB +Java maximum memory (-Xmx): 3 GB + +User name: nick +User home directory: /home/nick +User working directory: /home/nick/Documents/Programming/Brainfuck/BPFU/bfpcompiler +User country: US +User language: en +User locale: en_US + +RDI_BASEROOT: /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado +HDI_APPROOT: /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1 +RDI_DATADIR: /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data +RDI_BINDIR: /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/bin + +Vivado preferences file: /home/nick/.Xilinx/Vivado/2023.1/vivado.xml +Vivado preferences directory: /home/nick/.Xilinx/Vivado/2023.1/ +Vivado layouts directory: /home/nick/.Xilinx/Vivado/2023.1/data/layouts +PlanAhead jar file: /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/lib/classes/planAhead.jar +Vivado log file: /home/nick/Documents/Programming/Brainfuck/BPFU/bfpcompiler/vivado.log +Vivado journal file: /home/nick/Documents/Programming/Brainfuck/BPFU/bfpcompiler/vivado.jou +Engine tmp dir: ./.Xil/Vivado-33785-lilith +Non-Default Parameters: [] + +Xilinx & AMD Environment Variables +-------------------------------------------------------------------------------------------- +RDI_APPROOT: /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1 +RDI_BASEROOT: /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado +RDI_BINROOT: /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/bin +RDI_BUILD: yes +RDI_DATADIR: /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data +RDI_INSTALLROOT: /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx +RDI_INSTALLVER: 2023.1 +RDI_JAVA_PLATFORM: +RDI_JAVA_VERSION: 17.0.3_7 +RDI_LIBDIR: /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/lib/lnx64.o/Default:/run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/lib/lnx64.o +RDI_OPT_EXT: .o +RDI_PATCHROOT: +RDI_PLATFORM: lnx64 +RDI_PREPEND_PATH: /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/ids_lite/ISE/bin/lin64 +RDI_PROG: /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/bin/unwrapped/lnx64.o/vivado +RDI_SESSION_INFO: /home/nick/Documents/Programming/Brainfuck/BPFU/bfpcompiler:lilith_1696512018_33730 +RDI_SHARED_DATA: /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/SharedData/2023.1/data +RDI_TPS_ROOT: /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/tps/lnx64 +RDI_USE_JDK17: True +SHELL: /usr/bin/zsh +XILINX: /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/ids_lite/ISE +XILINX_DSP: /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/ids_lite/ISE +XILINX_HLS: /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vitis_HLS/2023.1 +XILINX_PLANAHEAD: /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1 +XILINX_VITIS: +XILINX_VIVADO: /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1 +XILINX_VIVADO_HLS: /run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1 + + +GUI allocated memory: 512 MB +GUI max memory: 4,072 MB +Engine allocated memory: 1,339 MB + +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. + +*/ + +// TclEventType: START_GUI +// Tcl Message: start_gui +// HMemoryUtils.trashcanNow. Engine heap size: 1,351 MB. GUI used memory: 71 MB. Current time: 10/5/23, 3:21:16 PM CEST +// WARNING: HEventQueue.dispatchEvent() is taking 1001 ms. +// WARNING: HEventQueue.dispatchEvent() is taking 1001 ms. +selectList(PAResourceQtoS.SyntheticaGettingStartedView_RECENT_PROJECTS, "/home/nick/brainfuck/brainfuck.xpr", 0); // b.c +// Opening Vivado Project: /home/nick/brainfuck/brainfuck.xpr. Version: Vivado v2023.1 +// TclEventType: DEBUG_PROBE_SET_CHANGE +// TclEventType: FLOW_ADDED +// TclEventType: MSGMGR_MOVEMSG +// Tcl Message: open_project /home/nick/brainfuck/brainfuck.xpr +// TclEventType: FILE_SET_CHANGE +// TclEventType: FILE_SET_NEW +// TclEventType: RUN_COMPLETED +// TclEventType: RUN_STATUS_CHANGE +// TclEventType: RUN_COMPLETED +// TclEventType: RUN_STATUS_CHANGE +// TclEventType: RUN_CURRENT +// TclEventType: PROJECT_DASHBOARD_NEW +// TclEventType: PROJECT_DASHBOARD_GADGET_NEW +// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE +// TclEventType: PROJECT_DASHBOARD_GADGET_NEW +// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE +// TclEventType: PROJECT_DASHBOARD_GADGET_NEW +// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE +// TclEventType: PROJECT_DASHBOARD_GADGET_NEW +// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE +// TclEventType: PROJECT_DASHBOARD_GADGET_NEW +// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE +// TclEventType: PROJECT_DASHBOARD_GADGET_NEW +// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE +// TclEventType: PROJECT_NEW +// Tcl Message: open_project /home/nick/brainfuck/brainfuck.xpr +// Tcl Message: INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory '/home/nick/brainfuck/brainfuck.gen/sources_1'. +// Tcl Message: Scanning sources... Finished scanning sources +// Tcl Message: INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified +// TclEventType: PROJECT_NEW +// [GUI Memory]: 136 MB (+139641kb) [00:01:07] +// [Engine Memory]: 1,518 MB (+1439848kb) [00:01:07] +// [Engine Memory]: 1,649 MB (+58364kb) [00:01:08] +// WARNING: HEventQueue.dispatchEvent() is taking 4099 ms. +// Tcl Message: INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/run/media/nick/7434c313-c900-4822-b144-4e79f39ed56a/home/nick/AUR/vivado/pkg/vivado/opt/Xilinx/Vivado/2023.1/data/ip'. +// HMemoryUtils.trashcanNow. Engine heap size: 1,666 MB. GUI used memory: 76 MB. Current time: 10/5/23, 3:21:59 PM CEST +// TclEventType: FILE_SET_CHANGE +// Project name: brainfuck; location: /home/nick/brainfuck; part: xc7a100tcsg324-1 +// Tcl Message: open_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:08 . Memory (MB): peak = 7702.613 ; gain = 228.406 ; free physical = 667 ; free virtual = 12643 +// TclEventType: FILE_SET_CHANGE +dismissDialog("Open Project"); // bq +// [GUI Memory]: 147 MB (+4652kb) [00:01:12] +// Tcl Message: update_compile_order -fileset sources_1 +// TclEventType: DG_GRAPH_STALE +// TclEventType: FILE_SET_CHANGE +// Elapsed Time for: 'L.f': 42s +// [GUI Memory]: 154 MB (+153kb) [00:01:51] +// Elapsed Time for: 'L.f': 44s +// TclEventType: DG_GRAPH_STALE +// TclEventType: FILE_SET_CHANGE +// Elapsed Time for: 'L.f': 01m:18s +// Elapsed Time for: 'L.f': 01m:20s +// HMemoryUtils.trashcanNow. Engine heap size: 1,723 MB. GUI used memory: 76 MB. Current time: 10/5/23, 3:23:21 PM CEST +// Elapsed time: 96 seconds +selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Generate Bitstream]", 21, false); // f +// Run Command: PAResourceCommand.PACommandNames_RUN_BITGEN +selectButton(RDIResource.BaseDialog_YES, "Yes"); // a +dismissDialog("Synthesis is Out-of-date"); // u +// TclEventType: RUN_MODIFY +// TclEventType: RUN_RESET +// Tcl Message: reset_run synth_1 +// TclEventType: RUN_RESET +// TclEventType: RUN_STATUS_CHANGE +// TclEventType: RUN_RESET +// TclEventType: RUN_STATUS_CHANGE +// TclEventType: RUN_RESET +// TclEventType: RUN_MODIFY +// Tcl Message: INFO: [Project 1-1161] Replacing file /home/nick/brainfuck/brainfuck.srcs/utils_1/imports/synth_1/bfpu.dcp with file /home/nick/brainfuck/brainfuck.runs/synth_1/bfpu.dcp +// TclEventType: FILE_SET_CHANGE +selectButton(RDIResource.BaseDialog_OK, "OK"); // a +// 'ct' command handler elapsed time: 5 seconds +dismissDialog("Launch Runs"); // cw +// TclEventType: RUN_LAUNCH +// TclEventType: RUN_MODIFY +// TclEventType: RUN_STATUS_CHANGE +// TclEventType: RUN_MODIFY +// Tcl Message: launch_runs impl_1 -to_step write_bitstream -jobs 4 +// Tcl Message: [Thu Oct 5 15:23:43 2023] Launched synth_1... Run output will be captured here: /home/nick/brainfuck/brainfuck.runs/synth_1/runme.log [Thu Oct 5 15:23:43 2023] Launched impl_1... Run output will be captured here: /home/nick/brainfuck/brainfuck.runs/impl_1/runme.log +dismissDialog("Generate Bitstream"); // bq +// TclEventType: RUN_STATUS_CHANGE +// HMemoryUtils.trashcanNow. Engine heap size: 1,748 MB. GUI used memory: 77 MB. Current time: 10/5/23, 3:24:01 PM CEST +// [Engine Memory]: 1,747 MB (+15975kb) [00:03:17] +// TclEventType: RUN_FAILED +// TclEventType: RUN_STATUS_CHANGE +// TclEventType: RUN_STEP_COMPLETED +// TclEventType: RUN_STATUS_CHANGE +// Elapsed time: 56 seconds +selectButton(RDIResource.BaseDialog_OK, "OK"); // a +// Run Command: PAResourceCommand.PACommandNames_MESSAGE_WINDOW +dismissDialog("Synthesis Failed"); // Q.a +selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Synthesis, [Synth 8-428] missing elements in aggregate or subelement association [/home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/instructionMemory.vhd:23]. ]", 1, false); // u.d +messagesViewCrossProbe(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "src;-;/home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/instructionMemory.vhd;-;;-;16;-;line;-;23;-;;-;16;-;"); // u.d +// PAPropertyPanels.initPanels (instructionMemory.vhd) elapsed time: 0.3s +// HMemoryUtils.trashcanNow. Engine heap size: 1,783 MB. GUI used memory: 79 MB. Current time: 10/5/23, 3:24:51 PM CEST +// Elapsed time: 27 seconds +selectCodeEditor("instructionMemory.vhd", 263, 507); // ad +// Elapsed time: 100 seconds +expandTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Synthesis, [Synth 8-421] mismatched array sizes in rhs and lhs of assignment [/home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/instructionMemory.vhd:23]. ]", 2); // u.d +expandTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Synthesis, [Synth 8-285] failed synthesizing module 'instructionMemory' [/home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/instructionMemory.vhd:20]. ]", 4); // u.d +selectCodeEditor("instructionMemory.vhd", 249, 234); // ad +closeView(PAResourceOtoP.PAViews_CODE, "Code"); // F +selectButton(RDIResource.ConfirmSaveTextEditsDialog_NO, "No"); // a +dismissDialog("Text Changed"); // h +// TclEventType: DG_GRAPH_STALE +// TclEventType: FILE_SET_CHANGE +// Elapsed Time for: 'L.f': 05m:28s +// Elapsed time: 21 seconds +selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Run Synthesis]", 15, false); // f +// Run Command: PAResourceCommand.PACommandNames_RUN_SYNTHESIS +// TclEventType: RUN_MODIFY +// TclEventType: RUN_RESET +// TclEventType: RUN_STATUS_CHANGE +// TclEventType: RUN_RESET +// TclEventType: RUN_MODIFY +// Tcl Message: reset_run synth_1 +// Elapsed Time for: 'L.f': 05m:32s +selectButton(RDIResource.BaseDialog_OK, "OK"); // a +dismissDialog("Launch Runs"); // f +// TclEventType: RUN_LAUNCH +// TclEventType: RUN_MODIFY +// TclEventType: RUN_STATUS_CHANGE +// Tcl Message: launch_runs synth_1 -jobs 4 +// Tcl Message: [Thu Oct 5 15:27:31 2023] Launched synth_1... Run output will be captured here: /home/nick/brainfuck/brainfuck.runs/synth_1/runme.log +dismissDialog("Starting Design Runs"); // bq +// TclEventType: RUN_STATUS_CHANGE +// TclEventType: RUN_FAILED +// TclEventType: RUN_STATUS_CHANGE +// TclEventType: RUN_STEP_COMPLETED +// Elapsed time: 58 seconds +selectButton(RDIResource.BaseDialog_OK, "OK"); // a +// Run Command: PAResourceCommand.PACommandNames_MESSAGE_WINDOW +dismissDialog("Synthesis Failed"); // Q.a +selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Synthesis, [Synth 8-428] missing elements in aggregate or subelement association [/home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/instructionMemory.vhd:23]. ]", 1, false); // u.d +selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Synthesis, [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details. ]", 4, false); // u.d +selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Synthesis, [Synth 8-428] missing elements in aggregate or subelement association [/home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/instructionMemory.vhd:23]. ]", 1, false); // u.d +selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Synthesis, [Synth 8-428] missing elements in aggregate or subelement association [/home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/instructionMemory.vhd:23]. ]", 1, false, false, false, false, true, false); // u.d - Popup Trigger +// Elapsed time: 50 seconds +selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Synthesis, [Synth 8-421] mismatched array sizes in rhs and lhs of assignment [/home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/instructionMemory.vhd:23]. ]", 2, true); // u.d - Node +selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Synthesis, [Synth 8-421] mismatched array sizes in rhs and lhs of assignment [/home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/instructionMemory.vhd:23]. ]", 2, true, false, false, false, true, false); // u.d - Popup Trigger - Node +selectMenu(PAResourceItoN.MsgTreePanel_MESSAGE_SEVERITY, "Message Severity"); // al +// TclEventType: DG_GRAPH_STALE +// TclEventType: FILE_SET_CHANGE +// Elapsed Time for: 'L.f': 10m:54s +// Elapsed Time for: 'L.f': 11m:00s +// Elapsed time: 290 seconds +selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Generate Bitstream]", 21, false); // f +// Run Command: PAResourceCommand.PACommandNames_RUN_BITGEN +selectButton(RDIResource.BaseDialog_YES, "Yes"); // a +dismissDialog("No Implementation Results Available"); // u +// TclEventType: RUN_MODIFY +// TclEventType: RUN_RESET +// TclEventType: RUN_STATUS_CHANGE +// TclEventType: RUN_RESET +// TclEventType: RUN_MODIFY +// Tcl Message: reset_run synth_1 +selectButton(RDIResource.BaseDialog_OK, "OK"); // a +// 'ct' command handler elapsed time: 3 seconds +dismissDialog("Launch Runs"); // cw +// Tcl Message: launch_runs impl_1 -to_step write_bitstream -jobs 4 +// TclEventType: RUN_LAUNCH +// TclEventType: RUN_MODIFY +// TclEventType: RUN_STATUS_CHANGE +// TclEventType: RUN_MODIFY +// Tcl Message: [Thu Oct 5 15:34:29 2023] Launched synth_1... Run output will be captured here: /home/nick/brainfuck/brainfuck.runs/synth_1/runme.log [Thu Oct 5 15:34:29 2023] Launched impl_1... Run output will be captured here: /home/nick/brainfuck/brainfuck.runs/impl_1/runme.log +dismissDialog("Generate Bitstream"); // bq +// TclEventType: RUN_STATUS_CHANGE +// TclEventType: RUN_FAILED +// TclEventType: RUN_STATUS_CHANGE +// TclEventType: RUN_STEP_COMPLETED +// TclEventType: RUN_STATUS_CHANGE +// Elapsed time: 61 seconds +selectButton(RDIResource.BaseDialog_OK, "OK"); // a +// Run Command: PAResourceCommand.PACommandNames_MESSAGE_WINDOW +dismissDialog("Synthesis Failed"); // Q.a +// Elapsed time: 21 seconds +selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Synthesis, [Synth 8-10577] choice 'others' is not permitted when an aggregate expression is of the aggregate type [/home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/instructionMemory.vhd:23]. ]", 1, false); // u.d +messagesViewCrossProbe(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "src;-;/home/nick/Documents/Programming/Brainfuck/BPFU/fpga/src/instructionMemory.vhd;-;;-;16;-;line;-;23;-;;-;16;-;"); // u.d +// HMemoryUtils.trashcanNow. Engine heap size: 1,823 MB. GUI used memory: 80 MB. Current time: 10/5/23, 3:35:56 PM CEST +// Elapsed time: 10 seconds +selectCodeEditor("instructionMemory.vhd", 940, 277); // ad +selectCodeEditor("instructionMemory.vhd", 1027, 285); // ad +// TclEventType: DG_GRAPH_STALE +// TclEventType: FILE_SET_CHANGE +// [Engine Memory]: 1,843 MB (+9373kb) [00:15:18] +// Elapsed Time for: 'L.f': 14m:10s +// Elapsed Time for: 'L.f': 14m:14s +// Elapsed time: 54 seconds +selectCodeEditor("instructionMemory.vhd", 930, 284); // ad +// Elapsed time: 10 seconds +closeView(PAResourceOtoP.PAViews_CODE, "Code"); // F +// Elapsed time: 46 seconds +selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, bfpu(arch) (bfpu.vhd), instrMemory : instructionMemory(arch) (instructionMemory.vhd)]", 2, false); // E +selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, bfpu(arch) (bfpu.vhd), instrMemory : instructionMemory(arch) (instructionMemory.vhd)]", 2, false, false, false, false, false, true); // E - Double Click +closeView(PAResourceOtoP.PAViews_CODE, "Code"); // F +selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Run Synthesis]", 15, false); // f +// Run Command: PAResourceCommand.PACommandNames_RUN_SYNTHESIS +// TclEventType: RUN_MODIFY +// TclEventType: RUN_RESET +// TclEventType: RUN_STATUS_CHANGE +// TclEventType: RUN_RESET +// TclEventType: RUN_MODIFY +// Tcl Message: reset_run synth_1 +selectButton(RDIResource.BaseDialog_OK, "OK"); // a +dismissDialog("Launch Runs"); // f +// TclEventType: RUN_LAUNCH +// TclEventType: RUN_MODIFY +// TclEventType: RUN_STATUS_CHANGE +// Tcl Message: launch_runs synth_1 -jobs 4 +// Tcl Message: [Thu Oct 5 15:38:03 2023] Launched synth_1... Run output will be captured here: /home/nick/brainfuck/brainfuck.runs/synth_1/runme.log +dismissDialog("Starting Design Runs"); // bq +// TclEventType: RUN_STATUS_CHANGE +// TclEventType: DG_GRAPH_STALE +// TclEventType: FILE_SET_CHANGE +// Elapsed Time for: 'L.f': 16m:36s +// Elapsed Time for: 'L.f': 16m:40s +// Elapsed time: 42 seconds +selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Run Synthesis]", 15, false); // f +// Run Command: PAResourceCommand.PACommandNames_RUN_SYNTHESIS +selectButton("OptionPane.button", "OK"); // JButton +// TclEventType: RUN_MODIFY +// TclEventType: RUN_RESET +// Tcl Message: reset_run synth_1 +// TclEventType: RUN_STATUS_CHANGE +// TclEventType: RUN_RESET +// TclEventType: RUN_MODIFY +selectButton(RDIResource.BaseDialog_OK, "OK"); // a +dismissDialog("Launch Runs"); // f +// TclEventType: RUN_LAUNCH +// TclEventType: RUN_MODIFY +// TclEventType: RUN_STATUS_CHANGE +// Tcl Message: launch_runs synth_1 -jobs 4 +// Tcl Message: [Thu Oct 5 15:38:50 2023] Launched synth_1... Run output will be captured here: /home/nick/brainfuck/brainfuck.runs/synth_1/runme.log +// 'i' command handler elapsed time: 4 seconds +dismissDialog("Starting Design Runs"); // bq +// TclEventType: RUN_STATUS_CHANGE +selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, RTL Analysis, Open Elaborated Design]", 13, true); // f - Node +// Run Command: PAResourceCommand.PACommandNames_GOTO_RTL_DESIGN +// Tcl Message: synth_design -rtl -rtl_skip_mlo -name rtl_1 +// Tcl Message: Command: synth_design -rtl -rtl_skip_mlo -name rtl_1 Starting synth_design Using part: xc7a100tcsg324-1 Top: bfpu +// TclEventType: ELABORATE_START +// HMemoryUtils.trashcanNow. Engine heap size: 2,306 MB. GUI used memory: 81 MB. Current time: 10/5/23, 3:39:01 PM CEST +// TclEventType: ELABORATE_FINISH +// TclEventType: READ_XDC_FILE_START +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: POWER_CNS_STALE +// TclEventType: POWER_REPORT_STALE +// TclEventType: SDC_CONSTRAINT_ADD +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: LOC_CONSTRAINT_ADD +// TclEventType: SIGNAL_MODIFY +// TclEventType: READ_XDC_FILE_END +// TclEventType: FLOORPLAN_MODIFY +// TclEventType: DESIGN_NEW +// HMemoryUtils.trashcanNow. Engine heap size: 2,734 MB. GUI used memory: 81 MB. Current time: 10/5/23, 3:39:09 PM CEST +// [Engine Memory]: 2,737 MB (+840657kb) [00:18:21] +// TclEventType: DESIGN_NEW +// DeviceModel: Load Xgds SwingWorker Join Forever elapsed time: 0.6s +// TclEventType: HFED_INIT_ROUTE_STORAGE_COMPLETED +// WARNING: HEventQueue.dispatchEvent() is taking 3334 ms. +// TclEventType: CURR_DESIGN_SET +// Tcl Message: INFO: [Device 21-403] Loading part xc7a100tcsg324-1 +// Tcl Message: --------------------------------------------------------------------------------- +// Tcl Message: Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 8538.523 ; gain = 373.828 ; free physical = 593 ; free virtual = 10906 +// Tcl Message: --------------------------------------------------------------------------------- +// Tcl Message: --------------------------------------------------------------------------------- +// Tcl Message: Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 8640.492 ; gain = 475.797 ; free physical = 485 ; free virtual = 10803 +// Tcl Message: --------------------------------------------------------------------------------- +// Tcl Message: --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- +// Tcl Message: Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 8655.336 ; gain = 490.641 ; free physical = 471 ; free virtual = 10790 +// Tcl Message: --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- +// Tcl Message: Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 8655.336 ; gain = 490.641 ; free physical = 471 ; free virtual = 10790 +// Tcl Message: --------------------------------------------------------------------------------- +// Tcl Message: Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 8655.336 ; gain = 0.000 ; free physical = 471 ; free virtual = 10790 +// Tcl Message: INFO: [Project 1-570] Preparing netlist for logic optimization +// Tcl Message: Processing XDC Constraints Initializing timing engine Parsing XDC File [/home/nick/Documents/Programming/Brainfuck/BPFU/fpga/constrainits.xdc] Finished Parsing XDC File [/home/nick/Documents/Programming/Brainfuck/BPFU/fpga/constrainits.xdc] Completed Processing XDC Constraints +// Tcl Message: Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 8730.094 ; gain = 0.000 ; free physical = 444 ; free virtual = 10768 +// Tcl Message: INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. +// [GUI Memory]: 165 MB (+2987kb) [00:18:25] +// Tcl Message: RTL Elaboration Complete: : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 8831.926 ; gain = 667.230 ; free physical = 344 ; free virtual = 10682 +// Tcl Message: 23 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully +// Tcl Message: synth_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 8831.926 ; gain = 962.332 ; free physical = 344 ; free virtual = 10682 +// Tcl Message: INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] +// 'dA' command handler elapsed time: 19 seconds +// Elapsed time: 19 seconds +dismissDialog("Open Elaborated Design"); // bq +// TclEventType: RUN_COMPLETED +// TclEventType: RUN_STATUS_CHANGE +// TclEventType: RUN_STEP_COMPLETED +// [GUI Memory]: 184 MB (+11220kb) [00:19:25] +// Elapsed time: 67 seconds +selectButton(RDIResource.BaseDialog_OK, "OK"); // a +// Run Command: PAResourceCommand.PACommandNames_RUN_IMPLEMENTATION +selectButton(RDIResource.BaseDialog_OK, "OK"); // a +dismissDialog("Launch Runs"); // f +// TclEventType: RUN_LAUNCH +// TclEventType: RUN_MODIFY +// TclEventType: RUN_STATUS_CHANGE +// Tcl Message: launch_runs impl_1 -jobs 4 +// Tcl Message: [Thu Oct 5 15:40:25 2023] Launched impl_1... Run output will be captured here: /home/nick/brainfuck/brainfuck.runs/impl_1/runme.log +dismissDialog("Starting Design Runs"); // bq +// TclEventType: RUN_STATUS_CHANGE +// TclEventType: RUN_STEP_COMPLETED +// PAPropertyPanels.initPanels (state) elapsed time: 0.8s +// WARNING: HEventQueue.dispatchEvent() is taking 1384 ms. +// TclEventType: RUN_STEP_COMPLETED +// PAPropertyPanels.initPanels (s_in_i (RTL_MUX5)) elapsed time: 0.4s +// Elapsed time: 101 seconds +selectButton(PAResourceCommand.PACommandNames_ZOOM_IN, "Schematic_zoom_in"); // B +// Run Command: PAResourceCommand.PACommandNames_ZOOM_IN +selectButton(PAResourceCommand.PACommandNames_ZOOM_IN, "Schematic_zoom_in"); // B +// Run Command: PAResourceCommand.PACommandNames_ZOOM_IN +selectButton(PAResourceCommand.PACommandNames_ZOOM_OUT, "Schematic_zoom_out"); // B +// Run Command: PAResourceCommand.PACommandNames_ZOOM_OUT +// Elapsed time: 35 seconds +selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Project Summary", 0); // o +selectTab(PAResourceOtoP.ProjectSummaryUtilizationPanel_PROJECT_SUMMARY_UTILIZATION_PANEL_TABBED, PAResourceOtoP.ProjectSummaryUtilizationPanel_TABLE, "Table", 1); // e +selectTab(PAResourceOtoP.ProjectSummaryUtilizationGadget_PROJECT_SUMMARY_UTILIZATION_GADGET_TABBED, PAResourceOtoP.ProjectSummaryUtilizationGadget_POST_IMPLEMENTATION, "Post-Implementation", 1); // b +selectTab(PAResourceOtoP.ProjectSummaryUtilizationGadget_PROJECT_SUMMARY_UTILIZATION_GADGET_TABBED, PAResourceOtoP.ProjectSummaryUtilizationGadget_POST_SYNTHESIS, "Post-Synthesis", 0); // b diff --git a/fpga/.tmp_logic.md b/fpga/.tmp_logic.md new file mode 100644 index 0000000..1734fdb --- /dev/null +++ b/fpga/.tmp_logic.md @@ -0,0 +1,22 @@ +# Branch redesign + +## Skip new logic table + +| instruction | cell | skip | nest | | skip | +| ----------- | ---- | ---- | ---- | --- | ---- | +| [ | 0 | 0 | 0 | | 1 | +| [ | 0 | 1 | 0 | | 1 | +| [ | 0 | 1 | 1 | | 1 | +| [ | 1 | 0 | 0 | | 0 | +| [ | 1 | 1 | 0 | | 1 | +| [ | 1 | 1 | 1 | | 1 | + +> skip = not ( cell and (skip nor nest) ) + +| instruction | cell | skip | nest | | skip | +| ----------- | ---- | ---- | ---- | --- | ---- | +| ] | - | 0 | 0 | | 0 | +| ] | - | 1 | 0 | | 0 | +| ] | - | 1 | 1 | | 1 | + +> skip = skip and nest diff --git a/fpga/src/instructionMemory.vhd b/fpga/src/instructionMemory.vhd index 3860866..08dd7cc 100644 --- a/fpga/src/instructionMemory.vhd +++ b/fpga/src/instructionMemory.vhd @@ -20,7 +20,7 @@ end instructionMemory; architecture arch of instructionMemory is type imem is array(0 to 255) of std_logic_vector(2 downto 0); - signal memory : imem := (b"010", b"110", b"000", b"010", b"101", b"001", b"111", others => "000"); + signal memory : imem := (b"010",b"110",b"000",b"011",b"110",b"101",b"011",b"000",b"011",b"110",b"011",b"000",b"011",b"110",b"011",b"000",b"011",b"110",b"011",b"111",b"001",b"111",b"001",b"111",b"001",b"111",b"001",b"111",others=>"000"); begin -- Process clk_read -- clk_read : process (clk) -- runs only, when clk changed