From d27378e58f32f81bb35f1407b2ffe2d613c6aa0b Mon Sep 17 00:00:00 2001
From: yannickreiss <yannick.reiss@protonmail.ch>
Date: Tue, 26 Sep 2023 12:03:53 +0200
Subject: [PATCH] Implement cell memory

---
 fpga/src/bfpu.vhd       | 19 +++++++++++++++++++
 fpga/src/cellMemory.vhd | 42 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 61 insertions(+)

diff --git a/fpga/src/bfpu.vhd b/fpga/src/bfpu.vhd
index c85e7c4..06ffd13 100644
--- a/fpga/src/bfpu.vhd
+++ b/fpga/src/bfpu.vhd
@@ -50,6 +50,16 @@ architecture arch of bfpu is
         );
     end component;
 
+    component cellblock
+        port(
+            clk         :   in  std_logic;
+            enable      :   in  std_logic;
+            address     :   in  std_logic_vector(15 downto 0);
+            new_cell    :   in  std_logic_vector(7 downto 0);
+            old_cell    :   out std_logic_vector(7 downto 0)
+        );
+    end component;
+
     signal s_clk            :   std_logic;
     signal s_instrAddr      :   std_logic_vector(7 downto 0);
     signal s_instruction    :   std_logic_vector(2 downto 0);
@@ -95,4 +105,13 @@ begin
         old_ptr     => s_ptr_out
     );
 
+    cellblock_bf : cellblock
+    port map(
+        clk         => s_clk,
+        enable      => s_enable_cells,
+        address     => s_ptr_out,
+        new_cell    => s_cell_in,
+        old_cell    => s_cell_out
+    );
+
 end arch;
diff --git a/fpga/src/cellMemory.vhd b/fpga/src/cellMemory.vhd
index e69de29..b7da2d6 100644
--- a/fpga/src/cellMemory.vhd
+++ b/fpga/src/cellMemory.vhd
@@ -0,0 +1,42 @@
+-- cellMemory.vhd
+-- Created on: Di 26. Sep 11:39:10 CEST 2023
+-- Author(s): Yannick Reiß
+-- Content: Cell memory as part of brainfuck logic
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+-- Entity cellblock
+entity cellblock is
+
+    port(
+        clk         :   in  std_logic; -- clock with speed of board clock
+        enable      :   in  std_logic;
+        address     :   in  std_logic_vector(15 downto 0);
+        new_cell    :   in  std_logic_vector(7 downto 0);
+
+        old_cell    :   out std_logic_vector(7 downto 0)
+    );
+end cellblock;
+
+-- Architecture arch of cellblock: read on every clock cycle to cell.
+architecture arch of cellblock is
+    type empty is array(0 to 65536) of std_logic_vector(7 downto 0);
+
+    signal memory : empty := (others => (others => '0'));
+
+begin
+    -- Process clk_read
+    clk_read : process (clk) -- runs only, when clk changed
+    begin
+
+        if rising_edge(clk) and enable = '1' then
+            memory(to_integer(unsigned(address))) <= new_cell;
+        end if;
+
+    end process;
+
+    old_cell <= memory(to_integer(unsigned(address)));
+
+end arch;