Change instructions and testbench to test nested loops

2023-10-05 11:01:35 +02:00
parent 73d1db32c7
commit e27c8a4505
2 changed files with 4 additions and 5 deletions
--- a/fpga/tb/tb_bfpu.vhd
+++ b/fpga/tb/tb_bfpu.vhd
@@ -23,7 +23,7 @@ architecture implementation of bfpu_tb is
    -- output
    signal debug    :   std_logic_vector(7 downto 0);
    signal led      :   std_logic_vector(7 downto 0);
-    
+
    constant clk_period : time := 10 ns;

 begin
@@ -35,7 +35,7 @@ begin
            debug   =>  debug,
            led     =>  led);

-    sw      <= "00110011";
+    sw      <= "00001011";

    -- Clock process definitions
    clk_process :   process
@@ -56,4 +56,4 @@ begin
        wait;
    end process;

-end implementation ; -- implementation
+end implementation ; -- implementation