117 lines
3.9 KiB
Verilog
117 lines
3.9 KiB
Verilog
/*
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This file provides the mapping from the Wokwi modules to Verilog HDL
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It's only needed for Wokwi designs
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*/
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`define default_netname none
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// custom cells
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module reg_cell (input wire clk,
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input wire d,
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output wire q);
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reg register;
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always @(posedge clk) begin
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register = d;
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end
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assign q = register;
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endmodule // reg_cell
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// TinyTapeout cells
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module buffer_cell (
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input wire in,
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output wire out
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);
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assign out = in;
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endmodule
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module and_cell (
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input wire a,
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input wire b,
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output wire out
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);
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assign out = a & b;
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endmodule
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module or_cell (
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input wire a,
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input wire b,
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output wire out
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);
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assign out = a | b;
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endmodule
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module xor_cell (
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input wire a,
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input wire b,
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output wire out
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);
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assign out = a ^ b;
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endmodule
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module nand_cell (
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input wire a,
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input wire b,
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output wire out
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);
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assign out = !(a&b);
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endmodule
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module not_cell (
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input wire in,
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output wire out
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);
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assign out = !in;
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endmodule
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module mux_cell (
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input wire a,
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input wire b,
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input wire sel,
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output wire out
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);
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assign out = sel ? b : a;
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endmodule
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module dff_cell (
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input wire clk,
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input wire d,
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output reg q,
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output wire notq
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);
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assign notq = !q;
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always @(posedge clk)
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q <= d;
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endmodule
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module dffsr_cell (
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input wire clk,
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input wire d,
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input wire s,
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input wire r,
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output reg q,
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output wire notq
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);
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assign notq = !q;
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always @(posedge clk or posedge s or posedge r) begin
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if (r)
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q <= 0;
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else if (s)
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q <= 1;
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else
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q <= d;
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end
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endmodule
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