41 lines
1.0 KiB
VHDL
41 lines
1.0 KiB
VHDL
-- programCounter.vhd
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-- Created on: Di 26. Sep 12:45:10 CEST 2023
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-- Author(s): Yannick Reiß
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-- Content: Set and store program counter only. Logic entirely in branch!
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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-- Entity program_counter: set/store pc
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entity program_counter is
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port(
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clk : in std_logic;
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enable : in std_logic;
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jmp : in std_logic;
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pc_in : in std_logic_vector(7 downto 0);
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pc_out : out std_logic_vector(7 downto 0)
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);
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end program_counter;
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-- Architecture pc of program_counter:
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architecture pc of program_counter is
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signal pc_intern : std_logic_vector(7 downto 0) := (others => '0');
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begin
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-- Process count
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count : process (clk, enable) -- runs only, when clk, enable, jmp changed
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begin
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if rising_edge(clk) and enable = '1' then
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if jmp = '1' then
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pc_intern <= pc_in;
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else
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pc_intern <= std_logic_vector(unsigned(pc_intern) + 1);
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end if;
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end if;
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end process;
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pc_out <= pc_intern;
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end pc;
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