Yannick Reiß 8d340be824 Presentable program		2023-10-05 15:43:55 +02:00
..
src	Presentable program	2023-10-05 15:43:55 +02:00
tb	Change instructions and testbench to test nested loops	2023-10-05 11:01:35 +02:00
.tmp_logic.md	Presentable program	2023-10-05 15:43:55 +02:00
Makefile	Removed simulation duration to save time.	2023-10-05 12:30:40 +02:00
constrainits.xdc	First working implementation	2023-10-04 11:27:25 +02:00