39 lines
1.2 KiB
VHDL
39 lines
1.2 KiB
VHDL
-- instructionMemory.vhd
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-- Created on: Di 26. Sep 07:43:20 CEST 2023
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-- Author(s): Yannick Reiß
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-- Content: Instruction memory; Read and write operations are controlled externally.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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-- Entity instructionMemory: Currently ROM; TODO: Add write enable when implementing a bus.
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entity instructionMemory is
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port(
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instructionAddr : in std_logic_vector(7 downto 0); -- We start with 256 instructions
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instruction : out std_logic_vector(2 downto 0) -- instruction in current cell
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);
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end instructionMemory;
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-- Architecture arch of instructionMemory: read on every clock cycle to instruction.
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architecture arch of instructionMemory is
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type imem is array(0 to 255) of std_logic_vector(2 downto 0);
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signal memory : imem := (b"010", b"110", b"000", b"010", b"101", b"001", b"111", others => "000");
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begin
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-- Process clk_read
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-- clk_read : process (clk) -- runs only, when clk changed
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-- begin
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--
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-- if rising_edge(clk) then
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--
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-- instruction <= memory(to_integer(unsigned(instructionAddr)));
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--
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-- end if;
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-- end process;
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instruction <= memory(to_integer(unsigned(instructionAddr)));
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end arch;
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