diff --git a/src/Decoder.vhd b/src/Decoder.vhd
index 9ffe06b..19bac43 100644
--- a/src/Decoder.vhd
+++ b/src/Decoder.vhd
@@ -14,7 +14,8 @@ entity Decoder is
     RegOp1       : out std_logic_vector(3 downto 0);  -- Rj: first register to read
     RegOp2       : out std_logic_vector(3 downto 0);  -- Rk: second register to read
     RegWrite     : out std_logic_vector(3 downto 0);  -- Ri: the register to write to
-    BranchEnable : out std_logic
+    BranchEnable : out std_logic;
+    UncondJump   : out std_logic
     );
 end Decoder;
 
@@ -39,12 +40,13 @@ begin
       when others                                                                         => AluOpcd <= "1111";  -- if unsure, do nothing
     end case;
 
-    -- BranchEnable
-    case Instruction(3 downto 0) is
-      when "0001" | "1001" | "0100" | "1100" | "0101" | "1101" =>
-        BranchEnable <= '1';
-      when others => BranchEnable <= '0';
+    -- BranchEnable / unconditionaljumpop
+    case Instruction(5 downto 0) is
+      when "001110" | "101110" => BranchEnable <= '1';
+      when "011110" | "111110" => UncondJump   <= '1';
+      when others              => BranchEnable <= '0';
     end case;
+
   end process Decode;
 
 end Implementation;
diff --git a/src/branch.vhd b/src/branch.vhd
index 3de3d53..eba975c 100644
--- a/src/branch.vhd
+++ b/src/branch.vhd
@@ -12,6 +12,7 @@ entity Branch is
     AluResult    : in  std_logic_vector(15 downto 0);
     PC           : in  std_logic_vector(15 downto 0);
     PMNext       : in  std_logic_vector(15 downto 0);
+    UncondJump   : in  std_logic;
     JumpSuggest  : out std_logic;
     PCCalc       : out std_logic_vector(15 downto 0)
     );
@@ -22,6 +23,6 @@ architecture Implementation of Branch is
 begin
 
   PCCalc      <= std_logic_vector(signed(PC) + signed(PMNext));
-  JumpSuggest <= BranchEnable and AluResult(0);
+  JumpSuggest <= (BranchEnable and AluResult(0)) or UncondJump;
 
 end Implementation;
diff --git a/src/cpu16.vhd b/src/cpu16.vhd
index 01b66e9..da41efa 100644
--- a/src/cpu16.vhd
+++ b/src/cpu16.vhd
@@ -5,6 +5,12 @@
 library IEEE;
 use IEEE.std_logic_1164.all;
 
+-- TODO: Check I Type; Implement Load instructions
+-- TODO: Connect Register Data in
+-- TODO: Add RAM data and address input
+-- TODO: Connect I2C
+-- TODO: Add peripheral Memory block
+
 entity Cpu16 is
   port (
     Clk      : in    std_logic;
@@ -51,6 +57,7 @@ architecture Implementation of Cpu16 is
   signal BranchEnable        : std_logic                     := '0';
   signal JumpEnable          : std_logic                     := '0';
   signal State               : std_logic_vector(2 downto 0)  := (others => '0');
+  signal UnconditionalJumpOp : std_logic                     := '0';
 begin
 
   -- Include Entities
@@ -105,7 +112,8 @@ begin
       RegOp1       => RegisterRegister1,
       RegOp2       => RegisterRegister2,
       RegWrite     => RegisterRegisterW,
-      BranchEnable => BranchEnable
+      BranchEnable => BranchEnable,
+      UncondJump   => UnconditionalJumpOp
       );
 
   ImmUseless : entity work.Immediate(Implementation)
@@ -141,6 +149,7 @@ begin
       AluResult    => AluResult,
       PC           => InstructionCounter,
       PMNext       => NextInstruction,
+      UncondJump   => UnconditionalJumpOp,
       JumpSuggest  => Jump,
       PCCalc       => PcAddrCalc
       );
@@ -171,7 +180,6 @@ begin
     end case;
   end process AluSetInput;
 
-
   RGB <= Switches(7 downto 0);
 
 end Implementation;