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Removed Bus access from RAM

This commit is contained in:
= 2024-01-31 17:39:33 +01:00
parent fafd9320af
commit 8f14afc6ec
2 changed files with 17 additions and 49 deletions
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17
src/I2C.vhd
View File

@ -23,8 +23,18 @@ architecture Implementation of I2C is
signal Clk100k : std_logic := '0';
signal Clk100Counter : std_logic_vector(10 downto 0) := (others => '0');
signal PackageReg : std_logic_vector(11 downto 0) := (others => '0');
signal CpuAddress : std_logic_vector(7 downto 0) := (others => '0');
signal Message : std_logic_vector(7 downto 0) := (others => '0');
signal TargetAddress : std_logic_vector(7 downto 0) := (others => '0');
signal Command : std_logic_vector(7 downto 0) := (others => '0');
begin
-- Assign memory to sequences
CpuAddress <= ClientR(7 downto 0);
Message <= ClientR(15 downto 8);
TargetAddress <= ServerR(7 downto 0);
Command <= ServerR(15 downto 8);
ClkSplit100k : process(Clk)
begin
if rising_edge(Clk) then
@ -37,4 +47,11 @@ begin
end if;
end process ClkSplit100k;
ShiftRegister : process(Clk100k)
begin
if rising_edge(Clk) then
PackageReg <= SCL_In & PackageReg(11 downto 1);
end if;
end process ShiftRegister;
end Implementation;

49
src/ram.vhd
View File

@ -106,55 +106,6 @@ begin
BoardOutput <= DataIn;
end if;
-- handle I2CClient
if unsigned(AddrA) = 3 then
ReadA <= I2CClient;
else
case AddrA(15) is
when '1' =>
ReadA <= SReadA2;
when others => ReadA <= SReadA1;
end case;
end if;
if unsigned(AddrB) = 3 then
ReadB <= I2CClient;
else
case AddrB(15) is
when '1' =>
ReadB <= SReadB2;
when others => ReadB <= SReadB1;
end case;
end if;
-- handle I2CClient
if unsigned(AddrB) = 3 and WriteEnable = '1' then
I2CClient <= DataIn;
end if;
-- handle I2CServer
if unsigned(AddrA) = 4 then
ReadA <= I2CServer;
else
case AddrA(15) is
when '1' =>
ReadA <= SReadA2;
when others => ReadA <= SReadA1;
end case;
end if;
if unsigned(AddrB) = 4 then
ReadB <= I2CServer;
else
case AddrB(15) is
when '1' =>
ReadB <= SReadB2;
when others => ReadB <= SReadB1;
end case;
end if;
end if;
end process DirectIO;