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cpu16
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Add I2C to RAM

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Yannick Reiß 2024-01-31 12:47:15 +01:00
parent 9505af3467
commit c5853fc280
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GPG Key ID: 5A3AF456F0A0338C
2 changed files with 83 additions and 20 deletions
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7
src/cpu16.vhd
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@ -44,6 +44,8 @@ architecture Implementation of Cpu16 is
signal ImmediateValue : std_logic_vector(15 downto 0) := (others => '0');
signal PcEnable : std_logic := '0';
signal Jump : std_logic := '0';
signal I2CClient : std_logic_vector(15 downto 0) := (others => '0');
signal I2CServer : std_logic_vector(15 downto 0) := (others => '0');
begin
-- Include Entities
@ -57,7 +59,10 @@ begin
ReadA => RamReadA,
ReadB => RamReadB,
DirectIn => Switches,
DirectOut => LED
DirectOut => LED,
I2CClientIn => I2CClient,
I2CClientOut => I2CClient,
I2CServerOut => I2CServer
);
Alu : entity work.Alu(Implementation)

60
src/ram.vhd
View File

@ -16,7 +16,10 @@ entity Ram is
ReadA : out std_logic_vector(15 downto 0);
ReadB : out std_logic_vector(15 downto 0);
DirectIn : in std_logic_vector(15 downto 0);
DirectOut : out std_logic_vector(15 downto 0)
DirectOut : out std_logic_vector(15 downto 0);
I2CClientIn : in std_logic_vector(15 downto 0);
I2CClientOut : out std_logic_vector(15 downto 0);
I2CServerOut : out std_logic_vector(15 downto 0)
);
end Ram;
@ -37,6 +40,9 @@ architecture Behavioral of Ram is
signal BoardInput : std_logic_vector(15 downto 0) := (others => '0');
signal BoardOutput : std_logic_vector(15 downto 0) := (others => '0');
signal I2CClient : std_logic_vector(15 downto 0) := (others => '0');
signal I2CServer : std_logic_vector(15 downto 0) := (others => '0');
begin
block1 : entity work.Ram_Block(Memory)
@ -71,6 +77,7 @@ begin
if rising_edge(clk) then
-- must be treated as register
BoardInput <= DirectIn;
I2CClient <= I2CClientIn;
-- handle Directin
if unsigned(AddrA) = 1 then
@ -99,9 +106,60 @@ begin
BoardOutput <= DataIn;
end if;
-- handle I2CClient
if unsigned(AddrA) = 3 then
ReadA <= I2CClient;
else
case AddrA(15) is
when '1' =>
ReadA <= SReadA2;
when others => ReadA <= SReadA1;
end case;
end if;
if unsigned(AddrB) = 3 then
ReadB <= I2CClient;
else
case AddrB(15) is
when '1' =>
ReadB <= SReadB2;
when others => ReadB <= SReadB1;
end case;
end if;
-- handle I2CClient
if unsigned(AddrB) = 3 and WriteEnable = '1' then
I2CClient <= DataIn;
end if;
-- handle I2CServer
if unsigned(AddrA) = 4 then
ReadA <= I2CServer;
else
case AddrA(15) is
when '1' =>
ReadA <= SReadA2;
when others => ReadA <= SReadA1;
end case;
end if;
if unsigned(AddrB) = 4 then
ReadB <= I2CServer;
else
case AddrB(15) is
when '1' =>
ReadB <= SReadB2;
when others => ReadB <= SReadB1;
end case;
end if;
end if;
end process DirectIO;
DirectOut <= BoardOutput;
I2CClientOut <= I2CClient;
I2CServerOut <= I2CServer;
end Behavioral;