yannickreiss
/
cpu16
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Add I2C to RAM

This commit is contained in:
Yannick Reiß 2024-01-31 12:47:15 +01:00
parent 9505af3467
commit c5853fc280
No known key found for this signature in database
GPG Key ID: 5A3AF456F0A0338C
2 changed files with 83 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
src/cpu16.vhd
View File

@ -44,20 +44,25 @@ architecture Implementation of Cpu16 is
signal ImmediateValue : std_logic_vector(15 downto 0) := (others => '0');
signal PcEnable : std_logic := '0';
signal Jump : std_logic := '0';
signal I2CClient : std_logic_vector(15 downto 0) := (others => '0');
signal I2CServer : std_logic_vector(15 downto 0) := (others => '0');
begin
-- Include Entities
Ramblock : entity work.Ram(Behavioral)
port map(
Clk => Clk,
AddrA => RamAddrA,
AddrB => RamAddrB,
WriteEnable => RamWriteEnable,
DataIn => RamDataWrite,
ReadA => RamReadA,
ReadB => RamReadB,
DirectIn => Switches,
DirectOut => LED
Clk => Clk,
AddrA => RamAddrA,
AddrB => RamAddrB,
WriteEnable => RamWriteEnable,
DataIn => RamDataWrite,
ReadA => RamReadA,
ReadB => RamReadB,
DirectIn => Switches,
DirectOut => LED,
I2CClientIn => I2CClient,
I2CClientOut => I2CClient,
I2CServerOut => I2CServer
);
Alu : entity work.Alu(Implementation)

78
src/ram.vhd
View File

@ -8,15 +8,18 @@ use IEEE.numeric_std.all;
entity Ram is
port(
Clk : in std_logic;
AddrA : in std_logic_vector(15 downto 0);
AddrB : in std_logic_vector(15 downto 0);
WriteEnable : in std_logic;
DataIn : in std_logic_vector(15 downto 0);
ReadA : out std_logic_vector(15 downto 0);
ReadB : out std_logic_vector(15 downto 0);
DirectIn : in std_logic_vector(15 downto 0);
DirectOut : out std_logic_vector(15 downto 0)
Clk : in std_logic;
AddrA : in std_logic_vector(15 downto 0);
AddrB : in std_logic_vector(15 downto 0);
WriteEnable : in std_logic;
DataIn : in std_logic_vector(15 downto 0);
ReadA : out std_logic_vector(15 downto 0);
ReadB : out std_logic_vector(15 downto 0);
DirectIn : in std_logic_vector(15 downto 0);
DirectOut : out std_logic_vector(15 downto 0);
I2CClientIn : in std_logic_vector(15 downto 0);
I2CClientOut : out std_logic_vector(15 downto 0);
I2CServerOut : out std_logic_vector(15 downto 0)
);
end Ram;
@ -37,6 +40,9 @@ architecture Behavioral of Ram is
signal BoardInput : std_logic_vector(15 downto 0) := (others => '0');
signal BoardOutput : std_logic_vector(15 downto 0) := (others => '0');
signal I2CClient : std_logic_vector(15 downto 0) := (others => '0');
signal I2CServer : std_logic_vector(15 downto 0) := (others => '0');
begin
block1 : entity work.Ram_Block(Memory)
@ -71,6 +77,7 @@ begin
if rising_edge(clk) then
-- must be treated as register
BoardInput <= DirectIn;
I2CClient <= I2CClientIn;
-- handle Directin
if unsigned(AddrA) = 1 then
@ -99,9 +106,60 @@ begin
BoardOutput <= DataIn;
end if;
-- handle I2CClient
if unsigned(AddrA) = 3 then
ReadA <= I2CClient;
else
case AddrA(15) is
when '1' =>
ReadA <= SReadA2;
when others => ReadA <= SReadA1;
end case;
end if;
if unsigned(AddrB) = 3 then
ReadB <= I2CClient;
else
case AddrB(15) is
when '1' =>
ReadB <= SReadB2;
when others => ReadB <= SReadB1;
end case;
end if;
-- handle I2CClient
if unsigned(AddrB) = 3 and WriteEnable = '1' then
I2CClient <= DataIn;
end if;
-- handle I2CServer
if unsigned(AddrA) = 4 then
ReadA <= I2CServer;
else
case AddrA(15) is
when '1' =>
ReadA <= SReadA2;
when others => ReadA <= SReadA1;
end case;
end if;
if unsigned(AddrB) = 4 then
ReadB <= I2CServer;
else
case AddrB(15) is
when '1' =>
ReadB <= SReadB2;
when others => ReadB <= SReadB1;
end case;
end if;
end if;
end process DirectIO;
DirectOut <= BoardOutput;
DirectOut <= BoardOutput;
I2CClientOut <= I2CClient;
I2CServerOut <= I2CServer;
end Behavioral;