80 lines
2.2 KiB
VHDL
80 lines
2.2 KiB
VHDL
-- control.vhd
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-- Date: Wed Jan 31 17:41:32 2024
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-- Author: Yannick Reiß
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-- E-Mail: schnick@nickr.eu
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity Control is
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port (
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Clk : in std_logic;
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Instruction : in std_logic_vector(15 downto 0);
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JumpSuggest : in std_logic;
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EnablePC : out std_logic;
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EnableReg : out std_logic;
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EnableRam : out std_logic;
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EnableRegs : out std_logic;
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EnableJump : out std_logic;
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StateOut : out std_logic_vector(2 downto 0)
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);
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end Control;
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architecture Implementation of Control is
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signal State : std_logic_vector(2 downto 0) := (others => '0');
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signal CouldJump : std_logic := '0';
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begin
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StateInterator : process(Clk)
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begin
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if rising_edge(Clk) then
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case State is
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when "000" | "101" => State <= "001"; -- Init / Write Back
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when "001" => State <= "010"; -- Instruction Fetch
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when "010" => State <= "011"; -- Decode
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when "011" => State <= "100"; -- Operand Fetch
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when "100" => State <= "101"; -- Execute
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when others => State <= "000"; -- ERROR
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end case;
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end if;
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end process StateInterator;
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SetEnableSignals : process(Instruction(3 downto 0), State)
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begin
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case State is
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when "101" =>
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EnablePC <= '1';
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case Instruction(3 downto 0) is
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when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" | "1000" | "1001" | "1010" | "1011" =>
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EnableRam <= '0';
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CouldJump <= '0';
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EnableRegs <= '1';
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when "1100" =>
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EnableRam <= '1';
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CouldJump <= '0';
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EnableRegs <= '0';
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when "1110" =>
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EnableRam <= '0';
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CouldJump <= '1';
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EnableRegs <= '0';
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when others =>
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EnableRam <= '0';
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CouldJump <= '0';
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EnableRegs <= '0';
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end case;
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when others =>
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EnablePC <= '0';
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EnableRam <= '0';
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CouldJump <= '0';
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EnableRegs <= '0';
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end case;
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end process SetEnableSignals;
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EnableJump <= CouldJump and JumpSuggest;
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StateOut <= State;
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end Implementation;
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