41 lines
1.1 KiB
VHDL
41 lines
1.1 KiB
VHDL
-- I2C.vhd
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-- Date: Wed Jan 31 13:05:40 2024
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-- Author: Yannick Reiß
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-- E-Mail: schnick@nickr.eu
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity I2C is
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port (
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Clk : in std_logic;
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SDA_In : in std_logic;
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SCL_In : in std_logic;
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ClientR : in std_logic_vector(15 downto 0);
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ServerR : in std_logic_vector(15 downto 0);
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SDA_Out : out std_logic;
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SCL_Out : out std_logic;
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ClientW : out std_logic_vector(15 downto 0)
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);
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end I2C;
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architecture Implementation of I2C is
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signal Clk100k : std_logic := '0';
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signal Clk100Counter : std_logic_vector(10 downto 0) := (others => '0');
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signal PackageReg : std_logic_vector(11 downto 0) := (others => '0');
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begin
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ClkSplit100k : process(Clk)
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begin
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if rising_edge(Clk) then
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if unsigned(Clk100Counter) >= 500 then
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Clk100Counter <= (others => '0');
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Clk100k <= not Clk100k;
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else
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Clk100Counter <= std_logic_vector(unsigned(Clk100Counter) + 1);
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end if;
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end if;
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end process ClkSplit100k;
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end Implementation;
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