29 lines
740 B
VHDL
29 lines
740 B
VHDL
-- branch.vhd
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-- Date: Thu Feb 1 06:03:29 2024
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-- Author: Yannick Reiß
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-- E-Mail: schnick@nickr.eu
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity Branch is
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port (
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BranchEnable : in std_logic;
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AluResult : in std_logic_vector(15 downto 0);
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PC : in std_logic_vector(15 downto 0);
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PMNext : in std_logic_vector(15 downto 0);
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UncondJump : in std_logic;
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JumpSuggest : out std_logic;
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PCCalc : out std_logic_vector(15 downto 0)
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);
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end Branch;
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architecture Implementation of Branch is
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begin
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PCCalc <= std_logic_vector(signed(PC) + signed(PMNext));
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JumpSuggest <= (BranchEnable and AluResult(0)) or UncondJump;
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end Implementation;
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