From 706051c4e0f452af9ed9761ea317fc708648b690 Mon Sep 17 00:00:00 2001
From: yannickreiss <yannick.reiss@protonmail.ch>
Date: Sun, 27 Aug 2023 16:46:52 +0200
Subject: [PATCH] Add Verilog snippet

---
 UltiSnips/verilog.snippets | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/UltiSnips/verilog.snippets b/UltiSnips/verilog.snippets
index 677fd39..d6e7028 100644
--- a/UltiSnips/verilog.snippets
+++ b/UltiSnips/verilog.snippets
@@ -42,3 +42,11 @@ endsnippet
 snippet ,double "set bus to size of a double word" A
 [63:0]$0
 endsnippet
+
+snippet module "Add module declaration" b
+module ${1:MODULE_NAME} (
+	$2
+);
+	$0
+endmodule // $1
+endsnippet