Yannick Reiß 583d6f9790 Update Verilog snippets		2023-08-26 08:21:47 +02:00
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de.utf-8.add	Update Verilog snippets	2023-08-26 08:21:47 +02:00
de.utf-8.add.spl	Update Verilog snippets	2023-08-26 08:21:47 +02:00
en.utf-8.add	Update Verilog snippets	2023-08-26 08:21:47 +02:00
en.utf-8.add.spl	Update Verilog snippets	2023-08-26 08:21:47 +02:00