From 695ed94236eba00f1fb0c1a790597f947caf24c6 Mon Sep 17 00:00:00 2001
From: yannickreiss <yannick.reiss@protonmail.ch>
Date: Mon, 4 Mar 2024 15:58:47 +0100
Subject: [PATCH] Stack implementation (Faulty)

---
 stack.vhd     | 71 +++++++++++++++++++++++++++++++++++++
 tb_stack.vhdl | 98 +++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 169 insertions(+)
 create mode 100644 stack.vhd
 create mode 100644 tb_stack.vhdl

diff --git a/stack.vhd b/stack.vhd
new file mode 100644
index 0000000..4be286b
--- /dev/null
+++ b/stack.vhd
@@ -0,0 +1,71 @@
+-- stack.vhd
+-- Date:   Mon Mar  4 09:40:36 2024
+-- Author:    Yannick Reiß
+-- E-Mail:    yannick.reiss@nickr.eu
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity stack is
+  port(
+    clk            : in  std_logic;     -- clk
+    enable         : in  std_logic;     -- on enable do op
+    op             : in  std_logic;     -- 0 = pop, 1 = push
+    data_store     : in  std_logic_vector(7 downto 0);  -- Byte to store
+    alert_overflow : out std_logic;  -- Signal when stack pointer is at limit
+    data_out       : out std_logic_vector(7 downto 0);  -- Byte from memory
+    block_parity   : out std_logic      -- parity over all bits
+    );
+end stack;
+
+architecture Mem of stack is
+  type memblock is array(0 to 63) of std_logic_vector(7 downto 0);
+
+  signal memory          : memblock                     := (others => (others => '0'));
+  signal stack_pointer   : std_logic_vector(5 downto 0) := (others => '0');
+  signal s_parity        : std_logic                    := '0';
+begin
+
+  mem_logic : process(all)
+  begin
+    if rising_edge(clk) then
+      if enable = '1' then
+
+        -- read or write memory
+        if op = '1' then
+          memory(to_integer(unsigned(stack_pointer))) <= data_store;
+        end if;
+
+        -- adjust stack pointer
+        if op = '1' then
+        -- stack_pointer <= std_logic_vector(unsigned(stack_pointer) + 1);
+        else
+        -- stack_pointer <= std_logic_vector(unsigned(stack_pointer) - 1);
+        end if;
+      end if;
+    end if;
+  end process mem_logic;
+
+  set_parity : process(memory, s_parity)
+  begin
+    for i in memory'range loop
+      for j in memory(i)'range loop
+        s_parity <= s_parity xor memory(i)(j);
+      end loop;
+    end loop;
+  end process set_parity;
+
+  set_limit : process(clk)
+  begin
+    if rising_edge(clk) then
+      if unsigned(stack_pointer) = 63 then
+        alert_overflow <= '1';
+      else
+        alert_overflow <= '0';
+      end if;
+    end if;
+  end process set_limit;
+
+  block_parity <= s_parity;
+  data_out     <= memory(to_integer(unsigned(stack_pointer) - 1));
+end Mem;
diff --git a/tb_stack.vhdl b/tb_stack.vhdl
new file mode 100644
index 0000000..c31e04e
--- /dev/null
+++ b/tb_stack.vhdl
@@ -0,0 +1,98 @@
+-- tb_stack.vhdl
+-- Date:   Mon Mar  4 10:07:49 2024
+-- Author:    Yannick Reiß
+-- E-Mail:    yannick.reiss@nickr.eu
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library std;
+use std.textio.all;
+
+library work;
+
+entity stack_tb is
+end stack_tb;
+
+architecture Testbench of stack_tb is
+
+  signal clk            : std_logic;
+  constant clk_period   : time                         := 10 ns;
+  signal enable         : std_logic                    := '0';
+  signal op             : std_logic                    := '0';
+  signal data_store     : std_logic_vector(7 downto 0) := "00110011";
+  signal alert_overflow : std_logic                    := '0';
+  signal data_out       : std_logic_vector(7 downto 0) := (others => '0');
+  signal block_parity   : std_logic                    := '0';
+begin
+
+  uut : entity work.stack(Mem)
+    port map (
+      clk            => clk,
+      enable         => enable,
+      op             => op,
+      data_store     => data_store,
+      alert_overflow => alert_overflow,
+      data_out       => data_out,
+      block_parity   => block_parity
+      );
+
+  clk_process : process
+  begin
+    clk <= '0';
+    wait for clk_period/2;
+    clk <= '1';
+    wait for clk_period/2;
+  end process;
+
+  testing : process
+    variable lineBuffer : line;
+  begin
+    wait until rising_edge(clk);
+    write(lineBuffer, string'("Starting the simulator"));
+    writeline(output, lineBuffer);
+
+    -- Try pushing something
+    data_store <= "00011101";
+    op         <= '1';
+    enable     <= '1';
+    wait for 5 ns;
+    enable     <= '0';
+
+    -- Push
+    wait for 5 ns;
+    data_store <= "00011110";
+    op         <= '1';
+    enable     <= '1';
+    wait for 5 ns;
+    enable     <= '0';
+
+    -- Push
+    wait for 5 ns;
+    data_store <= "10011110";
+    op         <= '1';
+    enable     <= '1';
+    wait for 5 ns;
+    enable     <= '0';
+
+    -- Pop
+    wait for 5 ns;
+    op     <= '0';
+    enable <= '1';
+    wait for 5 ns;
+    enable <= '0';
+
+    -- Pop
+    wait for 5 ns;
+    op     <= '0';
+    enable <= '1';
+    wait for 5 ns;
+    enable <= '0';
+
+    write(lineBuffer, string'("End of simulator"));
+    writeline(output, lineBuffer);
+
+    wait;
+  end process;
+
+end Testbench;