diff --git a/Makefile b/Makefile
index 9f05f87..0cd18bb 100644
--- a/Makefile
+++ b/Makefile
@@ -6,13 +6,13 @@ PARTS	=	alu
 all: $(PARTS)
 
 %: %.vhd tb_%.vhd
-	$(CHDL) -a $(FLAGS)
-	$(CHDL) -e $(FLAGS)
-	$(CHDL) -r $(FLAGS) --wave=$@.ghw --stop-time=$(STOP)
+	$(CHDL) -a $(FLAGS) $^
+	$(CHDL) -e $(FLAGS) $@
+	$(CHDL) -r $(FLAGS) $@ --wave=$@.ghw --stop-time=$(STOP)
 
 clean:
-	find . -name '*.o' -exec rm -r {}\;
-	find . -name '*.cf' -exec rm -r {}\;
-	find . -name '*.ghw' -exec rm -r {}\;
+	rm *.o
+	rm *.cf
+	rm *.ghw
 
-.PHONY: all clean
+.PHONY: all clean $(PARTS)
diff --git a/alu.vhd b/alu.vhd
index be510ea..a6dc6e9 100644
--- a/alu.vhd
+++ b/alu.vhd
@@ -8,11 +8,11 @@ use ieee.numeric_std.all;
 
 -- Entity ALU: Calculate result
 entity ALU is
-    port(
-        operator	:	in	std_logic_vector(3 downto 0);
-		operand1    :   in  std_logic_vector(2 downto 0);
-        operand2    :   in  std_logic_vector(2 downto 0);
-        result      :   out std_logic_vector(7 downto 0)
+  port(
+    operator : in  std_logic_vector(5 downto 0);
+    operand1 : in  std_logic_vector(7 downto 0);
+    operand2 : in  std_logic_vector(7 downto 0);
+    result   : out std_logic_vector(7 downto 0)
     );
 end ALU;
 
@@ -20,9 +20,43 @@ end ALU;
 architecture Logic of ALU is
 
 begin
-    -- Process Calculate
-    Calculate : process (all) -- runs only, when all changed
-    begin
-    end process;
-
+  -- Process Calculate
+  Calculate : process (all)
+  begin
+    case operator is
+      when "000000" => result <= not operand1;   -- Not op1
+      when "000100" =>
+        for i in operand1'range loop
+          result(i) <= operand1(i) xor operand2(i);
+        end loop;  -- Par op1
+      when "001000" => result <= (others => '0');        -- Cnt op1
+      when "001101" => result <= operand1 and operand2;  -- And op1
+      when "010001" => result <= operand1 or operand2;   -- Or op1
+      when "010101" => result <= operand1 xor operand2;  -- Xor op1
+      when "011001" => result <= operand2;       -- Mov op1
+      when "011101" => result <= std_logic_vector(to_stdlogicvector(to_bitvector(operand1) sll to_integer(unsigned(operand2))));  -- Sl op1
+      when "100001" => result <= std_logic_vector(to_stdlogicvector(to_bitvector(operand1) srl to_integer(unsigned(operand2))));  -- Sr op1
+      when "000010" => result <= std_logic_vector(unsigned(operand1) + unsigned(operand2));  -- Add op1
+      when "000110" => result <= std_logic_vector(signed(operand1) - signed(operand2));  -- Sub op1
+      when "000011" =>
+        if unsigned(operand1) = unsigned(operand2) then
+          result <= "00000001";
+        else
+          result <= (others => '0');
+        end if;  -- Seq op1
+      when "000111" =>
+        if signed(operand1) < signed(operand2) then
+          result <= "00000001";
+        else
+          result <= (others => '0');
+        end if;  -- Slt op1
+      when "001011" =>
+        if unsigned(operand1) < unsigned(operand2) then
+          result <= "00000001";
+        else
+          result <= (others => '0');
+        end if;  -- Sltu op1
+      when others => result <= (others => '0');  -- Default to nop operation
+    end case;
+  end process;
 end Logic;
diff --git a/tb_alu.vhd b/tb_alu.vhd
index e69de29..262c42c 100644
--- a/tb_alu.vhd
+++ b/tb_alu.vhd
@@ -0,0 +1,75 @@
+-- tb_alu.vhd
+-- Date:   Sun Mar  3 09:47:29 2024
+-- Author:    Yannick Reiß
+-- E-Mail:    yannick.reiss@nickr.eu
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library std;
+use std.textio.all;
+
+library work;
+
+entity alu_tb is
+end alu_tb;
+
+architecture Testbench of alu_tb is
+
+  signal clk          : std_logic;
+  constant clk_period : time                         := 10 ns;
+  signal operator     : std_logic_vector(5 downto 0) := (others => '0');
+  signal operand1     : std_logic_vector(7 downto 0) := (others => '0');
+  signal operand2     : std_logic_vector(7 downto 0) := (others => '0');
+  signal result       : std_logic_vector(7 downto 0) := (others => '0');
+begin
+
+  uut : entity work.alu(Logic)
+    port map (
+      operator => operator,
+      operand1 => operand1,
+      operand2 => operand2,
+      result   => result
+      );
+
+  clk_process : process
+  begin
+    clk <= '0';
+    wait for clk_period/2;
+    clk <= '1';
+    wait for clk_period/2;
+  end process;
+
+  testing : process
+    variable lineBuffer : line;
+  begin
+    wait until rising_edge(clk);
+    write(lineBuffer, string'("Starting the simulator"));
+    writeline(output, lineBuffer);
+
+    -- Testcases
+    for i in 1 to 20 loop
+      operand1 <= std_logic_vector(to_unsigned(i, 8));
+      operand2 <= std_logic_vector(to_unsigned(20 - i, 8));
+      operator <= "001101";
+      wait for 10 ns;
+
+      -- Not
+      if not (result = not operand1) then
+        write(lineBuffer, string'("Error on Not"));
+        writeline(output, lineBuffer);
+      end if;
+
+      -- Parity
+      operator <= "000100";
+      wait for 10 ns;
+
+    end loop;
+
+    write(lineBuffer, string'("end of simulator"));
+    writeline(output, lineBuffer);
+
+    wait;
+  end process;
+
+end Testbench;