yannickreiss/stackprocessor
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Fix the testbench

Browse Source
This commit is contained in:
yannickreiss
2024-03-04 07:58:08 +01:00
parent 275853931b
commit dd78c0e4e4
4 changed files with 217 additions and 89 deletions
Download Patch File Download Diff File Expand all files Collapse all files

33
alu.vhd
View File

@@ -18,21 +18,32 @@ end ALU;
-- Architecture Logic of ALU: Asynchronous calculation
architecture Logic of ALU is
signal parity : std_logic := '0';
signal count : std_logic_vector(7 downto 0) := (others => '0');
begin
set_parity : process(operand1(0), operand1(1), operand1(2), operand1(3),
operand1(4), operand1(5), operand1(6), operand1(7))
begin
parity <= operand1(7) xor operand1(6) xor operand1(5) xor operand1(4) xor operand1(3) xor operand1(2) xor operand1(1) xor operand1(0);
end process set_parity;
set_count : process(all)
begin
count <= std_logic_vector(unsigned(count));
end process set_count;
-- Process Calculate
Calculate : process (all)
Calculate : process (operand1, operand2, operator, parity)
begin
case operator is
when "000000" => result <= not operand1; -- Not op1
when "000100" =>
for i in operand1'range loop
result(i) <= operand1(i) xor operand2(i);
end loop; -- Par op1
when "001000" => result <= (others => '0'); -- Cnt op1
when "001101" => result <= operand1 and operand2; -- And op1
when "010001" => result <= operand1 or operand2; -- Or op1
when "010101" => result <= operand1 xor operand2; -- Xor op1
when "000000" => result <= operand1 xor "11111111"; -- Not op1
when "000100" => result <= "0000000" & parity; -- Par op1
when "001000" => result <= (others => '0'); -- Cnt op1
when "001101" => result <= operand1 and operand2; -- And op1
when "010001" => result <= operand1 or operand2; -- Or op1
when "010101" => result <= operand1 xor operand2; -- Xor op1
when "011001" => result <= operand2; -- Mov op1
when "011101" => result <= std_logic_vector(to_stdlogicvector(to_bitvector(operand1) sll to_integer(unsigned(operand2)))); -- Sl op1
when "100001" => result <= std_logic_vector(to_stdlogicvector(to_bitvector(operand1) srl to_integer(unsigned(operand2)))); -- Sr op1