-- stack.vhd -- Date: Mon Mar 4 09:40:36 2024 -- Author: Yannick Reiß -- E-Mail: yannick.reiss@nickr.eu library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity stack is port( clk : in std_logic; -- clk enable : in std_logic; -- on enable do op op : in std_logic; -- 0 = pop, 1 = push data_store : in std_logic_vector(7 downto 0); -- Byte to store alert_overflow : out std_logic; -- Signal when stack pointer is at limit data_out : out std_logic_vector(7 downto 0); -- Byte from memory block_parity : out std_logic -- parity over all bits ); end stack; architecture Mem of stack is type memblock is array(0 to 63) of std_logic_vector(7 downto 0); signal memory : memblock := (others => (others => '0')); signal stack_pointer : std_logic_vector(5 downto 0) := (others => '0'); signal s_parity : std_logic := '0'; begin mem_logic : process(all) begin if rising_edge(clk) then if enable = '1' then -- read or write memory if op = '1' then memory(to_integer(unsigned(stack_pointer))) <= data_store; end if; -- adjust stack pointer if op = '1' then -- stack_pointer <= std_logic_vector(unsigned(stack_pointer) + 1); else -- stack_pointer <= std_logic_vector(unsigned(stack_pointer) - 1); end if; end if; end if; end process mem_logic; set_parity : process(memory, s_parity) begin for i in memory'range loop for j in memory(i)'range loop s_parity <= s_parity xor memory(i)(j); end loop; end loop; end process set_parity; set_limit : process(clk) begin if rising_edge(clk) then if unsigned(stack_pointer) = 63 then alert_overflow <= '1'; else alert_overflow <= '0'; end if; end if; end process set_limit; block_parity <= s_parity; data_out <= memory(to_integer(unsigned(stack_pointer) - 1)); end Mem;