-- tb_stack.vhdl
-- Date:   Mon Mar  4 10:07:49 2024
-- Author:    Yannick Reiß
-- E-Mail:    yannick.reiss@nickr.eu
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

library std;
use std.textio.all;

library work;

entity stack_tb is
end stack_tb;

architecture Testbench of stack_tb is

  signal clk            : std_logic;
  constant clk_period   : time                         := 10 ns;
  signal enable         : std_logic                    := '0';
  signal op             : std_logic                    := '0';
  signal data_store     : std_logic_vector(7 downto 0) := "00110011";
  signal alert_overflow : std_logic                    := '0';
  signal data_out       : std_logic_vector(7 downto 0) := (others => '0');
  signal block_parity   : std_logic                    := '0';
begin

  uut : entity work.stack(Mem)
    port map (
      clk            => clk,
      enable         => enable,
      op             => op,
      data_store     => data_store,
      alert_overflow => alert_overflow,
      data_out       => data_out,
      block_parity   => block_parity
      );

  clk_process : process
  begin
    clk <= '0';
    wait for clk_period/2;
    clk <= '1';
    wait for clk_period/2;
  end process;

  testing : process
    variable lineBuffer : line;
  begin
    wait until rising_edge(clk);
    write(lineBuffer, string'("Starting the simulator"));
    writeline(output, lineBuffer);

    -- Try pushing something
    data_store <= "00011101";
    op         <= '1';
    enable     <= '1';
    wait for 5 ns;
    enable     <= '0';

    -- Push
    wait for 5 ns;
    data_store <= "00011110";
    op         <= '1';
    enable     <= '1';
    wait for 5 ns;
    enable     <= '0';

    -- Push
    wait for 5 ns;
    data_store <= "10011110";
    op         <= '1';
    enable     <= '1';
    wait for 5 ns;
    enable     <= '0';

    -- Pop
    wait for 5 ns;
    op     <= '0';
    enable <= '1';
    wait for 5 ns;
    enable <= '0';

    -- Pop
    wait for 5 ns;
    op     <= '0';
    enable <= '1';
    wait for 5 ns;
    enable <= '0';

    write(lineBuffer, string'("End of simulator"));
    writeline(output, lineBuffer);

    wait;
  end process;

end Testbench;