-- tb_alu.vhd
-- Date:   Sun Mar  3 09:47:29 2024
-- Author:    Yannick Reiß
-- E-Mail:    yannick.reiss@nickr.eu
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

library std;
use std.textio.all;

library work;

entity alu_tb is
end alu_tb;

architecture Testbench of alu_tb is

  signal clk          : std_logic;
  constant clk_period : time                         := 10 ns;
  signal operator     : std_logic_vector(5 downto 0) := (others => '0');
  signal operand1     : std_logic_vector(7 downto 0) := (others => '0');
  signal operand2     : std_logic_vector(7 downto 0) := (others => '0');
  signal result       : std_logic_vector(7 downto 0) := (others => '0');
begin

  uut : entity work.alu(Logic)
    port map (
      operator => operator,
      operand1 => operand1,
      operand2 => operand2,
      result   => result
      );

  clk_process : process
  begin
    clk <= '0';
    wait for clk_period/2;
    clk <= '1';
    wait for clk_period/2;
  end process;

  testing : process
    variable lineBuffer : line;
  begin
    wait until rising_edge(clk);
    write(lineBuffer, string'("Starting the simulator"));
    writeline(output, lineBuffer);

    -- Testcases
    for i in 1 to 20 loop
      operand1 <= std_logic_vector(to_unsigned(i, 8));
      operand2 <= std_logic_vector(to_unsigned(20 - i, 8));
      operator <= "001101";
      wait for 10 ns;

      -- Not
      if not (result = not operand1) then
        write(lineBuffer, string'("Error on Not"));
        writeline(output, lineBuffer);
      end if;

      -- Parity
      operator <= "000100";
      wait for 10 ns;

    end loop;

    write(lineBuffer, string'("end of simulator"));
    writeline(output, lineBuffer);

    wait;
  end process;

end Testbench;