-- regs.vhd
-- Date:   Mon Mar  4 16:49:33 2024
-- Author:    Yannick Reiß
-- E-Mail:    yannick.reiss@nickr.eu
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity regs is
  port map(
    clk          : in  std_logic;
    write_enable : in  std_logic;
    value_write  : in  std_logic_vector(7 downto 0);
    register1    : in  std_logic_vector(2 downto 0);
    register2    : in  std_logic_vector(2 downto 0);
    value_r1     : out std_logic_vector(7 downto 0);
    value_r2     : out std_logic_vector(7 downto 0)
    );
end regs;

architecture Implementation of regs is
  type regbench is array(0 to 7) of std_logic_vector(7 downto 0);

  signal registerblock : regbench := (others => (others => '0'));
begin

  -- react only on clock changes
  process (clk)                         -- runs only, when clk changed
  begin
    if rising_edge(clk) then
      -- check if write is enabled
      if to_integer(unsigned(write_enable)) = 1 then
        -- write data_in to wr_idx
        registerblock(to_integer(unsigned(register1))) <= value_write;
      end if;
    end if;
  end process;

  value_r1 <= registerblock(to_integer(unsigned(register1)));
  value_r2 <= registerblock(to_integer(unsigned(register2)));
end Implementation;