-- tb_regs.vhdl
-- Date:   Mon Mar  4 17:58:35 2024
-- Author:    Yannick Reiß
-- E-Mail:    yannick.reiss@nickr.eu
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

library work;

library std;
use std.textio.all;

entity regs_tb is
end regs_tb;

architecture testing of regs_tb is
  signal clk          : std_logic;
  constant clk_period : time := 10 ns;

  -- Inputs
  signal write_enable : std_logic;
  signal value_write  : std_logic_vector(7 downto 0);
  signal register1    : std_logic_vector(2 downto 0);
  signal register2    : std_logic_vector(2 downto 0);
  signal value_r1     : std_logic_vector(7 downto 0);
  signal value_r2     : std_logic_vector(7 downto 0);

begin

  uut : entity work.regs(Implementation)
    port map(
      clk          => clk,
      write_enable => write_enable,
      value_write  => value_write,
      register1    => register1,
      register2    => register2,
      value_r1     => value_r1,
      value_r2     => value_r2
      );

  clk_process : process                 -- runs always
  begin
    clk <= '0';
    wait for clk_period/2;
    clk <= '1';
    wait for clk_period/2;
  end process;
end testing;