63 lines
2.3 KiB
VHDL
63 lines
2.3 KiB
VHDL
-- alu.vhd
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-- Created on: Sa 2. Mär 15:48:05 CET 2024
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-- Author(s): Yannick Reiß
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-- Content: ALU entity
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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-- Entity ALU: Calculate result
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entity ALU is
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port(
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operator : in std_logic_vector(5 downto 0);
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operand1 : in std_logic_vector(7 downto 0);
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operand2 : in std_logic_vector(7 downto 0);
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result : out std_logic_vector(7 downto 0)
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);
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end ALU;
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-- Architecture Logic of ALU: Asynchronous calculation
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architecture Logic of ALU is
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begin
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-- Process Calculate
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Calculate : process (all)
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begin
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case operator is
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when "000000" => result <= not operand1; -- Not op1
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when "000100" =>
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for i in operand1'range loop
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result(i) <= operand1(i) xor operand2(i);
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end loop; -- Par op1
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when "001000" => result <= (others => '0'); -- Cnt op1
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when "001101" => result <= operand1 and operand2; -- And op1
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when "010001" => result <= operand1 or operand2; -- Or op1
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when "010101" => result <= operand1 xor operand2; -- Xor op1
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when "011001" => result <= operand2; -- Mov op1
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when "011101" => result <= std_logic_vector(to_stdlogicvector(to_bitvector(operand1) sll to_integer(unsigned(operand2)))); -- Sl op1
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when "100001" => result <= std_logic_vector(to_stdlogicvector(to_bitvector(operand1) srl to_integer(unsigned(operand2)))); -- Sr op1
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when "000010" => result <= std_logic_vector(unsigned(operand1) + unsigned(operand2)); -- Add op1
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when "000110" => result <= std_logic_vector(signed(operand1) - signed(operand2)); -- Sub op1
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when "000011" =>
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if unsigned(operand1) = unsigned(operand2) then
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result <= "00000001";
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else
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result <= (others => '0');
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end if; -- Seq op1
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when "000111" =>
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if signed(operand1) < signed(operand2) then
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result <= "00000001";
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else
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result <= (others => '0');
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end if; -- Slt op1
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when "001011" =>
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if unsigned(operand1) < unsigned(operand2) then
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result <= "00000001";
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else
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result <= (others => '0');
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end if; -- Sltu op1
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when others => result <= (others => '0'); -- Default to nop operation
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end case;
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end process;
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end Logic;
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