From db3638be6580c9c5cb4b7f2945dcbc7a0d89cdd4 Mon Sep 17 00:00:00 2001 From: yannickreiss Date: Mon, 18 Mar 2024 10:58:46 +0100 Subject: [PATCH] Setup project --- docs/info.md | 8 +++-- info.yaml | 54 ++++++++++++++--------------- src/lights_out.v | 88 ++++++++++++++++++++++++++++++++++++++++++++++++ src/project.v | 24 ------------- 4 files changed, 120 insertions(+), 54 deletions(-) create mode 100644 src/lights_out.v delete mode 100644 src/project.v diff --git a/docs/info.md b/docs/info.md index ce1f04c..76812d9 100644 --- a/docs/info.md +++ b/docs/info.md @@ -9,12 +9,14 @@ You can also include images in this folder and reference them in the markdown. E ## How it works -Explain how your project works +Takes input from buttons and updates a led matrix. +The current state of the game is stored internally using registers. ## How to test -Explain how to use your project +Connect the chip to 9 buttons and 9 LEDs. +Press the buttons and try to deactivate all of the LEDs. ## External hardware -List external hardware used in your project (e.g. PMOD, LED display, etc), if any +clock, 9 LEDs, 9 buttons diff --git a/info.yaml b/info.yaml index f04da75..caac047 100644 --- a/info.yaml +++ b/info.yaml @@ -1,47 +1,47 @@ # Tiny Tapeout project information project: - title: "" # Project title - author: "" # Your name - discord: "" # Your discord username, for communication and automatically assigning you a Tapeout role (optional) - description: "" # One line description of what your project does + title: "Lights out" # Project title + author: "Yannick Reiß" # Your name + discord: "schnick_" # Your discord username, for communication and automatically assigning you a Tapeout role (optional) + description: "Lights out game." # One line description of what your project does language: "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc - clock_hz: 0 # Clock frequency in Hz (or 0 if not applicable) + clock_hz: 500 # Clock frequency in Hz (or 0 if not applicable) # How many tiles your design occupies? A single tile is about 167x108 uM. tiles: "1x1" # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2 # Your top module name must start with "tt_um_". Make it unique by including your github username: - top_module: "tt_um_example" - + top_module: "tt_yannickreiss_lights_out" + # List your project's source files here. Source files must be in ./src and you must list each source file separately, one per line: - source_files: - - "project.v" + source_files: + - "lights_out.v" # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins. pinout: # Inputs - ui[0]: "" - ui[1]: "" - ui[2]: "" - ui[3]: "" - ui[4]: "" - ui[5]: "" - ui[6]: "" - ui[7]: "" + ui[0]: "LED 1" + ui[1]: "LED 2" + ui[2]: "LED 3" + ui[3]: "LED 4" + ui[4]: "LED 5" + ui[5]: "LED 6" + ui[6]: "LED 7" + ui[7]: "LED 8" # Outputs - uo[0]: "" - uo[1]: "" - uo[2]: "" - uo[3]: "" - uo[4]: "" - uo[5]: "" - uo[6]: "" - uo[7]: "" + uo[0]: "LED 1" + uo[1]: "LED 2" + uo[2]: "LED 3" + uo[3]: "LED 4" + uo[4]: "LED 5" + uo[5]: "LED 6" + uo[6]: "LED 7" + uo[7]: "LED 8" # Bidirectional pins - uio[0]: "" - uio[1]: "" + uio[0]: "LED 9" + uio[1]: "LED 9" uio[2]: "" uio[3]: "" uio[4]: "" diff --git a/src/lights_out.v b/src/lights_out.v new file mode 100644 index 0000000..619223a --- /dev/null +++ b/src/lights_out.v @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2024 Your Name + * SPDX-License-Identifier: Apache-2.0 + */ + +`define default_netname none + +module tt_yannickreiss_lights_out ( + input wire [7:0] ui_in, // Dedicated inputs + output wire [7:0] uo_out, // Dedicated outputs + input wire [7:0] uio_in, // IOs: Input path + output wire [7:0] uio_out, // IOs: Output path + output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output) + input wire ena, // will go high when the design is enabled + input wire clk, // clock + input wire rst_n // reset_n - low to reset +); + + // All output pins must be assigned. If not used, assign to 0. + assign uo_out = ui_in + uio_in; // Example: ou_out is the sum of ui_in and uio_in + assign uio_out = 0; + assign uio_oe = 8'b00000010; + + // Matrix (input) + wire in1; + wire in2; + wire in3; + wire in4; + wire in5; + wire in6; + wire in7; + wire in8; + wire in9; + assign in1 = ui_in[0]; + assign in2 = ui_in[1]; + assign in3 = ui_in[2]; + assign in4 = ui_in[3]; + assign in5 = ui_in[4]; + assign in6 = ui_in[5]; + assign in7 = ui_in[6]; + assign in8 = ui_in[7]; + assign in9 = uio_in[0]; + + // Matrix (current field) + reg field1; + reg field2; + reg field3; + reg field4; + reg field5; + reg field6; + reg field7; + reg field8; + reg field9; + + // Matrix (output) + assign uo_out[0] = field1; + assign uo_out[1] = field2; + assign uo_out[2] = field3; + assign uo_out[3] = field4; + assign uo_out[4] = field5; + assign uo_out[5] = field6; + assign uo_out[6] = field7; + assign uo_out[7] = field8; + assign uio_out[0] = field9; + + always @(posedge clk) begin + if (ena == 1'b1) begin + if (rst_n == 1'b1) begin + + // Do act normal + + end + else begin + + // set new matrix in a pseudo random way + field1 <= 1'b0; + field2 <= 1'b0; + field3 <= 1'b0; + field4 <= 1'b0; + field5 <= 1'b1; + field6 <= 1'b0; + field7 <= 1'b0; + field8 <= 1'b0; + end + end + end + +endmodule diff --git a/src/project.v b/src/project.v deleted file mode 100644 index a8a9476..0000000 --- a/src/project.v +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (c) 2024 Your Name - * SPDX-License-Identifier: Apache-2.0 - */ - -`define default_netname none - -module tt_um_example ( - input wire [7:0] ui_in, // Dedicated inputs - output wire [7:0] uo_out, // Dedicated outputs - input wire [7:0] uio_in, // IOs: Input path - output wire [7:0] uio_out, // IOs: Output path - output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output) - input wire ena, // will go high when the design is enabled - input wire clk, // clock - input wire rst_n // reset_n - low to reset -); - - // All output pins must be assigned. If not used, assign to 0. - assign uo_out = ui_in + uio_in; // Example: ou_out is the sum of ui_in and uio_in - assign uio_out = 0; - assign uio_oe = 0; - -endmodule