From fa728e5d534f10101e322a144a0d5aca98268df8 Mon Sep 17 00:00:00 2001 From: yannickreiss Date: Mon, 18 Mar 2024 11:06:06 +0100 Subject: [PATCH] Test and project fix --- src/lights_out.v | 2 -- test/Makefile | 4 ++-- test/tb.v | 2 +- 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/src/lights_out.v b/src/lights_out.v index db91bb5..e035afa 100644 --- a/src/lights_out.v +++ b/src/lights_out.v @@ -17,8 +17,6 @@ module tt_um_yannickreiss_lights_out ( ); // All output pins must be assigned. If not used, assign to 0. - assign uo_out = ui_in + uio_in; // Example: ou_out is the sum of ui_in and uio_in - assign uio_out = 0; assign uio_oe = 8'b00000010; // Matrix (input) diff --git a/test/Makefile b/test/Makefile index 4413db2..0864963 100644 --- a/test/Makefile +++ b/test/Makefile @@ -5,7 +5,7 @@ SIM ?= icarus TOPLEVEL_LANG ?= verilog SRC_DIR = $(PWD)/../src -PROJECT_SOURCES = project.v +PROJECT_SOURCES = lights_out.v ifneq ($(GATES),yes) @@ -32,7 +32,7 @@ VERILOG_SOURCES += $(PWD)/gate_level_netlist.v endif # Include the testbench sources: -VERILOG_SOURCES += $(PWD)/tb.v +VERILOG_SOURCES += $(PWD)/tb.v TOPLEVEL = tb # MODULE is the basename of the Python test file diff --git a/test/tb.v b/test/tb.v index 2e86eb4..c742c38 100644 --- a/test/tb.v +++ b/test/tb.v @@ -23,7 +23,7 @@ module tb (); wire [7:0] uio_oe; // Replace tt_um_example with your module name: - tt_um_example user_project ( + tt_um_lights_out user_project ( // Include power ports for the Gate Level test: `ifdef GL_TEST