Init

Makefile

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+# Makefile for lut
+# Yannick Reiß
+
+# Variable section
+PARTS		=	lut
+CHDL		= ghdl
+FLAGS		=	--std=08
+SRC			=	src/lut.vhd
+MULTI		=	$(SRC) tb/tb_lut.vhd
+STOP		=	300ns
+
+ENTITY		=	lut_tb
+TARGETSRC	=	$(MULTI)
+PART			=	lut
+
+# Build all
+all: $(PARTS)
+
+# execute testbench
+$(PART): $(TARGETSRC)
+	$(CHDL) -a $(FLAGS) $(TARGETSRC)
+	$(CHDL) -e $(FLAGS) $(ENTITY)
+	$(CHDL) -r $(FLAGS) $(ENTITY) --vcd=$(ENTITY).vcd --stop-time=$(STOP)
+
+# project rules
+clean:
+	find . -name '*.o' -exec rm -r {} \;
+	find . -name '*.cf' -exec rm -r {} \;
+	find . -name '*.ghw' -exec rm -r {} \;
+	find . -name '*.vcd' -exec rm -r {} \;
+	rm $(ENTITY)
+
+.PHONY: all clean

src/lut.vhd

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+-- lut.vhd
+-- Created on: Mi 28. Dez 13:36:43 CET 2022
+-- Author(s): Yannick Reiß
+-- Content:  Entity lut
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+-- Entity lut: multiply two words
+entity lut is
+  port(
+    clk             :   in  std_logic;
+    input_vector    :   in  std_logic_vector(3 downto 0);
+    program_enable  :   in  std_logic;
+    truth_table     :   in  std_logic_vector(15 downto 0);
+    output_signal   :   out std_logic
+    );
+end lut;
+
+-- Architecture Behavior of lut: multiply two words
+architecture Behavior of lut is
+    signal internal_truth_table : std_logic_vector(15 downto 0) := (others => '0');
+begin
+
+    -- Process program
+    program : process (all) -- runs only, when all changed
+    begin
+        if rising_edge(clk) then
+            if program_enable = '1' then
+                internal_truth_table <= truth_table;
+            end if;
+        end if;
+    end process;
+
+    output_signal <= truth_table(to_integer(unsigned(input_vector)));
+
+end Behavior;

tb/tb_lut.vhd

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+-- tb_lut.vhd
+-- Created on: Mo 12. Dez 10:45:36 CET 2022
+-- Author(s): Yannick Reiss
+-- Content: Testbench for Taperead and Tapewrite
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library std;
+use std.textio.all;
+
+-- Entity lut_tb: Testing unit (wrapper)
+entity lut_tb is
+end lut_tb;
+
+-- Architecture  of : test read and write operations
+architecture testing of lut_tb is
+		-- Clock
+		signal clk : std_logic;
+		constant clk_period : time := 10 ns;
+
+		-- Inputs
+        signal vec_in : std_logic_vector(3 downto 0) := "0000";
+        signal prog_ena : std_logic := '0';
+        signal truth_table : std_logic_vector(15 downto 0) := (others => '0');
+
+		-- Outputs
+        signal sig_out : std_logic := '0';
+
+begin
+
+		-- Instantiate the Unit Under Test (UUT)
+		-- Entity work.lut(Behavior): Unit to test
+		uut : entity work.lut(Behavior)
+				port map (
+                    clk => clk,
+                    input_vector => vec_in,
+                    program_enable => prog_ena,
+                    truth_table => truth_table,
+                    output_signal => sig_out
+					);
+
+		-- Process clk_process  Clock process definitions
+		clk_process : process -- runs only, when  changed
+		begin
+				clk <= '0';
+				wait for clk_period/2;
+				clk <= '1';
+				wait for clk_period/2;
+		end process;
+
+		-- Process stim_proc
+		stim_proc : process -- runs only, when  changed
+		begin
+
+		-- wait for the frist rising edge
+		wait until rising_edge(clk);
+
+        -- Set up the LUT
+        truth_table <= "1111000000000000";
+        prog_ena <= '1';
+        wait for 5 ns;
+        prog_ena <= '0';
+        wait for 5 ns;
+
+        -- Test
+        vec_in <= "0000";
+        wait for 5 ns;
+
+        -- Test
+        vec_in <= "0001";
+        wait for 5 ns;
+
+        -- Test
+        vec_in <= "0010";
+        wait for 5 ns;
+
+        -- Test
+        vec_in <= "0011";
+        wait for 5 ns;
+
+        -- Test
+        vec_in <= "0100";
+        wait for 5 ns;
+
+        -- Test
+        vec_in <= "0101";
+        wait for 5 ns;
+
+        -- Test
+        vec_in <= "0110";
+        wait for 5 ns;
+
+        -- Test
+        vec_in <= "0111";
+        wait for 5 ns;
+
+        -- Test
+        vec_in <= "1000";
+        wait for 5 ns;
+
+        -- Test
+        vec_in <= "1001";
+        wait for 5 ns;
+
+        -- Test
+        vec_in <= "1010";
+        wait for 5 ns;
+
+        -- Test
+        vec_in <= "1011";
+        wait for 5 ns;
+
+        -- Test
+        vec_in <= "1100";
+        wait for 5 ns;
+
+        -- Test
+        vec_in <= "1101";
+        wait for 5 ns;
+
+        -- Test
+        vec_in <= "1110";
+        wait for 5 ns;
+
+        -- Test
+        vec_in <= "1111";
+        wait for 5 ns;
+
+		-- Testing memory
+				wait for 5 ns;
+				wait;
+		end process;
+
+end ;