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Reset in Register

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yannickreiss
2024-08-08 08:04:29 +02:00
parent 8b5b3095a0
commit 59cb94480e
1 changed files with 10 additions and 14 deletions
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12
src/registers.vhd
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@@ -40,8 +40,11 @@ architecture structure of registers is
begin begin
-- react only on clock changes -- react only on clock changes
process (clk) -- runs only, when clk changed process (clk, reset) -- runs only, when clk changed
begin begin
if falling_edge(reset) then
registerbench <= initRegs;
else
if rising_edge(clk) then if rising_edge(clk) then
-- check if write is enabled -- check if write is enabled
if to_integer(unsigned(write_enable)) = 1 then if to_integer(unsigned(write_enable)) = 1 then
@@ -50,13 +53,6 @@ begin
end if; end if;
registerbench(0) <= std_logic_vector(to_unsigned(0, wordWidth)); registerbench(0) <= std_logic_vector(to_unsigned(0, wordWidth));
end if; end if;
end process;
-- reset if reset is activated
process (reset)
begin
if falling_edge(reset) then
registerbench <= initRegs;
end if; end if;
end process; end process;