Implement reset of the processor

src/cpu.vhd

@@ -29,6 +29,7 @@ architecture implementation of cpu is
   component pc
     port(
       clk       : in  std_logic;        -- Clock input for timing
+      reset     : in  std_logic;
       en_pc     : in  one_bit;          -- activates PC
       addr_calc : in  ram_addr_t;       -- Address from ALU
       doJump    : in  one_bit;          -- Jump to Address
@@ -66,6 +67,7 @@ architecture implementation of cpu is
   component registers
     port(
       clk          : in  std_logic;     -- input for clock (control device)
+      reset        : in  std_logic;
       en_reg_wb    : in  one_bit;       -- enable register write back (?)
       data_in      : in  word;          -- Data to be written into the register
       wr_idx       : in  reg_idx;       -- register to write to
@@ -133,8 +135,8 @@ architecture implementation of cpu is
   signal X_addr_calc : ram_addr_t;
 
   -- Clock signals
-  signal reset  : std_logic;
-  signal locked : std_logic;
+  signal reset  : std_logic := '0';
+  signal locked : std_logic := '0';
 
 -------------------------
 -- additional ALU signals
@@ -151,6 +153,7 @@ begin
 
   -- External assignments
   s_clock             <= clk;
+  reset               <= rst;
   ram_enable_writing  <= s_ram_enable;
   instruction_pointer <= s_instAddr;
   data_address        <= s_data_in_addr;
@@ -170,6 +173,7 @@ begin
   registers_RISCV : registers
     port map(
       clk          => s_clock,
+      reset        => reset,
       en_reg_wb    => s_reg_wb_enable,
       data_in      => reg_data_in,
       wr_idx       => s_idx_wr,
@@ -190,6 +194,7 @@ begin
   pc_RISCV : pc
     port map(
       clk       => s_clock,
+      reset     => reset,
       en_pc     => s_pc_enable,
       addr_calc => X_addr_calc,
       doJump    => s_pc_jump_enable,
@@ -243,7 +248,6 @@ begin
       when others => aluIn1 <= s_reg_data1;
     end case;
 
-    -- TODO: why line from pc to alu inp1?
     -- connect input 2
     case s_opcode is
       when uADDI | uSLTI | uSLTIU | uXORI | uORI | uANDI => aluIn2 <= s_immediate;
@@ -313,7 +317,7 @@ begin
   end process;
 
   -- pc cycle control
-  pc_cycle_control : process(s_clock)
+  pc_cycle_control : process(s_clock, reset)
   begin
     if rising_edge(s_clock) then
       case s_cycle_cnt is
@@ -323,6 +327,10 @@ begin
         when stEXEC => s_cycle_cnt <= stWB;
         when others => s_cycle_cnt <= stIF;
       end case;
+    else
+      if falling_edge(reset) then
+        s_cycle_cnt <= stIF;
+      end if;
     end if;
   end process pc_cycle_control;
 

src/pc.vhd

@@ -12,35 +12,44 @@ use work.riscv_types.all;
 -- Entity PC: entity defining the pins and ports of the programmcounter
 entity pc is
   port (clk       : in  std_logic;      -- Clock input for timing
+        reset     : in  std_logic;
         en_pc     : in  one_bit;        -- activates PC
         addr_calc : in  ram_addr_t;     -- Address from ALU
         doJump    : in  one_bit;        -- Jump to Address
         addr      : out ram_addr_t      -- Address to Decoder
-    );
+        );
 
 end PC;
 
 
 architecture pro_count of pc is
-    signal addr_out : ram_addr_t := (others => '0');
-    signal addr_out_plus : ram_addr_t := (others => '0');
+  signal addr_out      : ram_addr_t := (others => '0');
+  signal addr_out_plus : ram_addr_t := (others => '0');
 begin
   process (clk)
   begin
     if rising_edge(clk) then
       if en_pc = "1" then
         -- count 
-        if doJump = "1" then 
-            addr_out <= addr_calc;
+        if doJump = "1" then
+          addr_out <= addr_calc;
         -- jump
         else
-            addr_out <= addr_out_plus;
+          addr_out <= addr_out_plus;
         end if;
       end if;
     end if;
   end process;
-  
+
+  process (reset)
+  begin
+    if falling_edge(reset) then
+      addr_out      <= (others => '0');
+      addr_out_plus <= (others => '0');
+    end if;
+  end process;
+
   addr_out_plus <= (std_logic_vector(to_unsigned(to_integer(unsigned(addr_out)) + 4, ram_addr_size)));
-  addr <= addr_out;
-  
+  addr          <= addr_out;
+
 end pro_count;

src/registers.vhd

@@ -22,6 +22,7 @@ entity registers is
     generic (initRegs : regFile := (others => (others => '0')));
     port(
         clk          : in  std_logic;   -- input for clock (control device)
+        reset        : in  std_logic;
         en_reg_wb    : in  one_bit;     -- enable register write back (?)
         data_in      : in  word;        -- Data to be written into the register
         wr_idx       : in  reg_idx;     -- register to write to
@@ -50,8 +51,17 @@ begin
             registerbench(0) <= std_logic_vector(to_unsigned(0, wordWidth));
         end if;
     end process;
+
+    -- reset if reset is activated
+    process (reset)
+    begin
+        if falling_edge(reset) then
+            registerbench <= initRegs;
+        end if;
+    end process;
+
     -- read from both reading registers
-    r1_out  <= registerbench(to_integer(unsigned(r1_idx)));
-    r2_out  <= registerbench(to_integer(unsigned(r2_idx)));
+    r1_out <= registerbench(to_integer(unsigned(r1_idx)));
+    r2_out <= registerbench(to_integer(unsigned(r2_idx)));
 
 end structure;