Reset in Register

src/cpu.vhd

@@ -327,10 +327,9 @@ begin
         when stEXEC => s_cycle_cnt <= stWB;
         when others => s_cycle_cnt <= stIF;
       end case;
-    else
-      if falling_edge(reset) then
-        s_cycle_cnt <= stIF;
-      end if;
+    end if;
+    if falling_edge(reset) then
+      s_cycle_cnt <= stIF;
     end if;
   end process pc_cycle_control;
 

src/pc.vhd

@@ -26,26 +26,22 @@ architecture pro_count of pc is
   signal addr_out      : ram_addr_t := (others => '0');
   signal addr_out_plus : ram_addr_t := (others => '0');
 begin
-  process (clk)
-  begin
-    if rising_edge(clk) then
-      if en_pc = "1" then
-        -- count 
-        if doJump = "1" then
-          addr_out <= addr_calc;
-        -- jump
-        else
-          addr_out <= addr_out_plus;
-        end if;
-      end if;
-    end if;
-  end process;
-
-  process (reset)
+  process (clk, reset)
   begin
     if falling_edge(reset) then
-      addr_out      <= (others => '0');
-      addr_out_plus <= (others => '0');
+      addr_out <= (others => '0');
+    else
+      if rising_edge(clk) then
+        if en_pc = "1" then
+          -- count 
+          if doJump = "1" then
+            addr_out <= addr_calc;
+          -- jump
+          else
+            addr_out <= addr_out_plus;
+          end if;
+        end if;
+      end if;
     end if;
   end process;
 

src/registers.vhd

@@ -40,23 +40,19 @@ architecture structure of registers is
 begin
 
     -- react only on clock changes
-    process (clk)                       -- runs only, when clk changed
-    begin
-        if rising_edge(clk) then
-            -- check if write is enabled
-            if to_integer(unsigned(write_enable)) = 1 then
-                -- write data_in to wr_idx
-                registerbench(to_integer(unsigned(wr_idx))) <= data_in;
-            end if;
-            registerbench(0) <= std_logic_vector(to_unsigned(0, wordWidth));
-        end if;
-    end process;
-
-    -- reset if reset is activated
-    process (reset)
+    process (clk, reset)                -- runs only, when clk changed
     begin
         if falling_edge(reset) then
             registerbench <= initRegs;
+        else
+            if rising_edge(clk) then
+                -- check if write is enabled
+                if to_integer(unsigned(write_enable)) = 1 then
+                    -- write data_in to wr_idx
+                    registerbench(to_integer(unsigned(wr_idx))) <= data_in;
+                end if;
+                registerbench(0) <= std_logic_vector(to_unsigned(0, wordWidth));
+            end if;
         end if;
     end process;