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brainfuck_processor
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Change instructions and testbench to test nested loops

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Yannick Reiß 2023-10-05 11:01:35 +02:00
parent 73d1db32c7
commit e27c8a4505
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2 changed files with 4 additions and 5 deletions
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3
fpga/src/instructionMemory.vhd
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@ -20,8 +20,7 @@ end instructionMemory;
architecture arch of instructionMemory is architecture arch of instructionMemory is
type imem is array(0 to 255) of std_logic_vector(2 downto 0); type imem is array(0 to 255) of std_logic_vector(2 downto 0);
-- +[+.] signal memory : imem := (b"010", b"110", b"000", b"010", b"101", b"001", b"111", others => "000");
signal memory : imem := (b"010", b"110", b"010", b"101", b"111", others => "000");
begin begin
-- Process clk_read -- Process clk_read
-- clk_read : process (clk) -- runs only, when clk changed -- clk_read : process (clk) -- runs only, when clk changed

2
fpga/tb/tb_bfpu.vhd
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@ -35,7 +35,7 @@ begin
debug => debug, debug => debug,
led => led); led => led);
sw <= "00110011"; sw <= "00001011";
-- Clock process definitions -- Clock process definitions
clk_process : process clk_process : process