Init leds with a definitive state
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b5dad1b5e6
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@ -8,195 +8,196 @@ use ieee.numeric_std.all;
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-- Entity bfpu: brainfuck processing unit
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entity bfpu is
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port(
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clk : in std_logic; -- board clock
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sw : in std_logic_vector(7 downto 0); -- Input for instruction ,
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debug : out std_logic_vector(7 downto 0); -- Value of currently selected logic cell.
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led : out std_logic_vector(7 downto 0) -- Output for instruction .
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port (
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clk : in std_logic; -- board clock
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sw : in std_logic_vector(7 downto 0); -- Input for instruction ,
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debug : out std_logic_vector(7 downto 0); -- Value of currently selected logic cell.
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led : out std_logic_vector(7 downto 0) -- Output for instruction .
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);
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end bfpu;
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end entity bfpu;
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-- Architecture arch of bfpu: setup and connect components
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architecture arch of bfpu is
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component instructionMemory
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port(
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instructionAddr : in std_logic_vector(7 downto 0);
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instruction : out std_logic_vector(2 downto 0)
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component instructionMemory is
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port (
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instructionAddr : in std_logic_vector(7 downto 0);
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instruction : out std_logic_vector(2 downto 0)
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);
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end component;
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end component instructionMemory;
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component alu
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port(
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instruction : in std_logic_vector(2 downto 0);
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old_cell : in std_logic_vector(7 downto 0);
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old_pointer : in std_logic_vector(15 downto 0);
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extern_in : in std_logic_vector(7 downto 0);
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component alu is
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port (
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instruction : in std_logic_vector(2 downto 0);
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old_cell : in std_logic_vector(7 downto 0);
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old_pointer : in std_logic_vector(15 downto 0);
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extern_in : in std_logic_vector(7 downto 0);
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new_cell : out std_logic_vector(7 downto 0);
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new_pointer : out std_logic_vector(15 downto 0);
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enable_cell : out std_logic;
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enable_ptr : out std_logic;
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extern_out : out std_logic_vector(7 downto 0)
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new_cell : out std_logic_vector(7 downto 0);
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new_pointer : out std_logic_vector(15 downto 0);
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enable_cell : out std_logic;
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enable_ptr : out std_logic;
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extern_out : out std_logic_vector(7 downto 0)
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);
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end component;
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end component alu;
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component ptr
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port(
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clk : in std_logic;
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enable_ptr : in std_logic;
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new_ptr : in std_logic_vector(15 downto 0);
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old_ptr : out std_logic_vector(15 downto 0)
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component ptr is
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port (
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clk : in std_logic;
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enable_ptr : in std_logic;
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new_ptr : in std_logic_vector(15 downto 0);
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old_ptr : out std_logic_vector(15 downto 0)
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);
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end component;
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end component ptr;
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component cellblock
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port(
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clk : in std_logic;
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enable : in std_logic;
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address : in std_logic_vector(15 downto 0);
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new_cell : in std_logic_vector(7 downto 0);
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old_cell : out std_logic_vector(7 downto 0)
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component cellblock is
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port (
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clk : in std_logic;
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enable : in std_logic;
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address : in std_logic_vector(15 downto 0);
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new_cell : in std_logic_vector(7 downto 0);
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old_cell : out std_logic_vector(7 downto 0)
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);
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end component;
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end component cellblock;
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component program_counter
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port(
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clk : in std_logic;
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enable : in std_logic;
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jmp : in std_logic;
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pc_in : in std_logic_vector(7 downto 0);
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pc_out : out std_logic_vector(7 downto 0)
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component program_counter is
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port (
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clk : in std_logic;
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enable : in std_logic;
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jmp : in std_logic;
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pc_in : in std_logic_vector(7 downto 0);
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pc_out : out std_logic_vector(7 downto 0)
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);
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end component;
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end component program_counter;
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component branch
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port(
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clk : in std_logic;
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state : in std_logic;
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instruction : in std_logic_vector(2 downto 0);
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instr_addr : in std_logic_vector(7 downto 0);
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cell_value : in std_logic_vector(7 downto 0);
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component branch is
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port (
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clk : in std_logic;
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state : in std_logic;
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instruction : in std_logic_vector(2 downto 0);
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instr_addr : in std_logic_vector(7 downto 0);
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cell_value : in std_logic_vector(7 downto 0);
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skip : out std_logic;
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jump : out std_logic;
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pc_enable : out std_logic;
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pc_out : out std_logic_vector(7 downto 0)
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skip : out std_logic;
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jump : out std_logic;
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pc_enable : out std_logic;
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pc_out : out std_logic_vector(7 downto 0)
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);
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end component;
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end component branch;
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signal s_clk : std_logic;
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signal s_in : std_logic_vector(7 downto 0) := (others => '0');
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signal s_out : std_logic_vector(7 downto 0) := (others => '0');
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signal s_clk : std_logic;
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signal s_in : std_logic_vector(7 downto 0) := (others => '0');
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signal s_out : std_logic_vector(7 downto 0) := (others => '0');
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signal s_led : std_logic_vector(7 downto 0) := (others => '0');
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signal s_instrAddr : std_logic_vector(7 downto 0) := "00000000";
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signal s_instruction : std_logic_vector(2 downto 0) := "000";
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signal s_instrAddr : std_logic_vector(7 downto 0) := "00000000";
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signal s_instruction : std_logic_vector(2 downto 0) := "000";
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signal s_cell_out : std_logic_vector(7 downto 0) := (others => '0');
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signal s_cell_in : std_logic_vector(7 downto 0) := (others => '0');
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signal s_ptr_out : std_logic_vector(15 downto 0) := (others => '0');
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signal s_ptr_in : std_logic_vector(15 downto 0) := (others => '0');
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signal s_cell_out : std_logic_vector(7 downto 0) := (others => '0');
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signal s_cell_in : std_logic_vector(7 downto 0) := (others => '0');
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signal s_ptr_out : std_logic_vector(15 downto 0) := (others => '0');
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signal s_ptr_in : std_logic_vector(15 downto 0) := (others => '0');
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signal s_enable_cells : std_logic := '0';
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signal s_enable_ptr : std_logic := '0';
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signal s_enable_cells : std_logic := '0';
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signal s_enable_ptr : std_logic := '0';
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signal s_enable_pc : std_logic := '1';
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signal s_jmp_pc : std_logic := '0';
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signal s_jmp_addr_pc : std_logic_vector(7 downto 0) := "00000000";
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signal s_enable_pc : std_logic := '1';
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signal s_jmp_pc : std_logic := '0';
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signal s_jmp_addr_pc : std_logic_vector(7 downto 0) := "00000000";
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signal s_skip : std_logic := '0';
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signal s_enable_cells_o : std_logic := '0';
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signal s_enable_ptr_o : std_logic := '0';
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signal s_skip : std_logic := '0';
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signal s_enable_cells_o : std_logic := '0';
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signal s_enable_ptr_o : std_logic := '0';
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signal processor_state : std_logic := '0'; -- 0: execute; 1: write back
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signal processor_state : std_logic := '0'; -- 0: execute; 1: write back
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begin
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-- clock and state logic
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s_clk <= clk;
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s_clk <= clk;
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-- Process state change state between execute and write back
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state : process (s_clk) -- runs only, when s_clk changed
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state: process (s_clk) is -- runs only, when s_clk changed
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begin
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if rising_edge(s_clk) then
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processor_state <= not processor_state;
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end if;
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end process;
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end process state;
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-- Process in_out set in- and output on clk high and exec/write back
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in_out : process (s_clk) -- runs only, when s_clk changed
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in_out: process (s_clk) is -- runs only, when s_clk changed
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begin
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if rising_edge(s_clk) then
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if processor_state = '1' then
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led <= s_out;
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s_led <= s_out;
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else
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s_in <= sw;
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s_in <= sw;
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end if;
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end if;
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end process;
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end process in_out;
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instrMemory : instructionMemory
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port map(
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instrMemory: component instructionMemory
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port map (
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instructionAddr => s_instrAddr,
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instruction => s_instruction
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instruction => s_instruction
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);
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alu_entity : alu
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port map(
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instruction => s_instruction,
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old_cell => s_cell_out,
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old_pointer => s_ptr_out,
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extern_in => s_in,
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alu_entity: component alu
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port map (
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instruction => s_instruction,
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old_cell => s_cell_out,
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old_pointer => s_ptr_out,
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extern_in => s_in,
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new_cell => s_cell_in,
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new_pointer => s_ptr_in,
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enable_cell => s_enable_cells_o,
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enable_ptr => s_enable_ptr_o,
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extern_out => s_out
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new_cell => s_cell_in,
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new_pointer => s_ptr_in,
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enable_cell => s_enable_cells_o,
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enable_ptr => s_enable_ptr_o,
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extern_out => s_out
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);
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ptr_bf : ptr
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port map(
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clk => s_clk,
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enable_ptr => s_enable_ptr,
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new_ptr => s_ptr_in,
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old_ptr => s_ptr_out
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ptr_bf: component ptr
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port map (
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clk => s_clk,
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enable_ptr => s_enable_ptr,
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new_ptr => s_ptr_in,
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old_ptr => s_ptr_out
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);
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cellblock_bf : cellblock
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port map(
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clk => s_clk,
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enable => s_enable_cells,
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address => s_ptr_out,
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new_cell => s_cell_in,
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old_cell => s_cell_out
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cellblock_bf: component cellblock
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port map (
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clk => s_clk,
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enable => s_enable_cells,
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address => s_ptr_out,
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new_cell => s_cell_in,
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old_cell => s_cell_out
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);
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pc : program_counter
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port map(
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clk => s_clk,
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enable => s_enable_pc and processor_state,
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jmp => s_jmp_pc,
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pc_in => s_jmp_addr_pc,
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pc_out => s_instrAddr
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pc: component program_counter
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port map (
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clk => s_clk,
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enable => s_enable_pc and processor_state,
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jmp => s_jmp_pc,
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pc_in => s_jmp_addr_pc,
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pc_out => s_instrAddr
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);
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branch_bf : branch
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port map(
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clk => s_clk,
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state => processor_state,
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instruction => s_instruction,
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instr_addr => s_instrAddr,
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cell_value => s_cell_out,
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skip => s_skip,
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jump => s_jmp_pc,
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pc_enable => s_enable_pc,
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pc_out => s_jmp_addr_pc
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branch_bf: component branch
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port map (
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clk => s_clk,
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state => processor_state,
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instruction => s_instruction,
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instr_addr => s_instrAddr,
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cell_value => s_cell_out,
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skip => s_skip,
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jump => s_jmp_pc,
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pc_enable => s_enable_pc,
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pc_out => s_jmp_addr_pc
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);
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s_enable_ptr <= not s_skip and s_enable_ptr_o and processor_state;
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s_enable_cells <= not s_skip and s_enable_cells_o and processor_state;
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debug <= s_cell_out;
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s_enable_ptr <= not s_skip and s_enable_ptr_o and processor_state;
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s_enable_cells <= not s_skip and s_enable_cells_o and processor_state;
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debug <= s_cell_out;
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led <= s_led;
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end arch;
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end architecture arch;
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