Implement clock splitter for I2C

src/I2C.vhd

@@ -10,17 +10,31 @@ entity I2C is
   port (
     Clk     : in  std_logic;
     SDA_In  : in  std_logic;
-    SDL_In  : in  std_logic;
+    SCL_In  : in  std_logic;
     ClientR : in  std_logic_vector(15 downto 0);
     ServerR : in  std_logic_vector(15 downto 0);
     SDA_Out : out std_logic;
-    SDL_Out : out std_logic;
+    SCL_Out : out std_logic;
     ClientW : out std_logic_vector(15 downto 0)
     );
 end I2C;
 
 architecture Implementation of I2C is
+  Clk100k       : std_logic                     := '0';
+  Clk100Counter : std_logic_vector(10 downto 0) := (others => '0');
 
 begin
 
+  ClkSplit100k : process(clk)
+  begin
+    if rising_edge(clk) then
+      if unsigned(Clk100Counter) >= 500 then
+        Clk100Counter <= (others => '0');
+        Clk100k       <= not Clk100k;
+      else
+        Clk100Counter <= std_logic_vector(unsigned(Clk100Counter) + 1);
+      end if;
+    end if;
+  end process ClkSplit100k;
+
 end Implementation;

src/cpu16.vhd

@@ -10,7 +10,7 @@ entity Cpu16 is
     Clk      : in    std_logic;
     Switches : in    std_logic_vector(15 downto 0);
     SDA      : inout std_logic;
-    SDL      : inout std_logic;
+    SCL      : inout std_logic;
     LED      : out   std_logic_vector(15 downto 0);
     RGB      : out   std_logic_vector(7 downto 0)
     );
@@ -122,11 +122,11 @@ begin
     port map(
       Clk     => Clk,
       SDA_In  => SDA,
-      SDL_In  => SDL,
+      SCL_In  => SCL,
       ClientR => I2CClient,
       ServerR => I2CServer,
       SDA_Out => SDA,
-      SDL_Out => SDL,
+      SCL_Out => SCL,
       ClientW => I2CClientOut
       );